📄 myfx2.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "MMCLK " "Info: Assuming node \"MMCLK\" is an undefined clock" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 35 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "MMCLK" } } } } } 0} } { } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK_2 " "Info: Detected ripple clock \"CLK_2\" as buffer" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 48 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK_2" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_4 " "Info: Detected ripple clock \"CLK_4\" as buffer" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 48 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK_4" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_8 " "Info: Detected ripple clock \"CLK_8\" as buffer" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 48 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK_8" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "MMCLK register register DREG\[9\] DREG\[15\] 275.03 MHz Internal " "Info: Clock \"MMCLK\" Internal fmax is restricted to 275.03 MHz between source register \"DREG\[9\]\" and destination register \"DREG\[15\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.266 ns + Longest register register " "Info: + Longest register to register delay is 2.266 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DREG\[9\] 1 REG LC_X2_Y14_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y14_N1; Fanout = 4; REG Node = 'DREG\[9\]'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "" { DREG[9] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 41 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.564 ns) 1.093 ns DREG\[9\]~165 2 COMB LC_X2_Y14_N1 2 " "Info: 2: + IC(0.529 ns) + CELL(0.564 ns) = 1.093 ns; Loc. = LC_X2_Y14_N1; Fanout = 2; COMB Node = 'DREG\[9\]~165'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "1.093 ns" { DREG[9] DREG[9]~165 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 41 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.171 ns DREG\[10\]~169 3 COMB LC_X2_Y14_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.171 ns; Loc. = LC_X2_Y14_N2; Fanout = 2; COMB Node = 'DREG\[10\]~169'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "0.078 ns" { DREG[9]~165 DREG[10]~169 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 41 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.249 ns DREG\[11\]~173 4 COMB LC_X2_Y14_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.249 ns; Loc. = LC_X2_Y14_N3; Fanout = 2; COMB Node = 'DREG\[11\]~173'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "0.078 ns" { DREG[10]~169 DREG[11]~173 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 41 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.427 ns DREG\[12\]~177 5 COMB LC_X2_Y14_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.427 ns; Loc. = LC_X2_Y14_N4; Fanout = 3; COMB Node = 'DREG\[12\]~177'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "0.178 ns" { DREG[11]~173 DREG[12]~177 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 41 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.266 ns DREG\[15\] 6 REG LC_X2_Y14_N7 2 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.266 ns; Loc. = LC_X2_Y14_N7; Fanout = 2; REG Node = 'DREG\[15\]'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "0.839 ns" { DREG[12]~177 DREG[15] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 41 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns 76.65 % " "Info: Total cell delay = 1.737 ns ( 76.65 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.529 ns 23.35 % " "Info: Total interconnect delay = 0.529 ns ( 23.35 % )" { } { } 0} } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "2.266 ns" { DREG[9] DREG[9]~165 DREG[10]~169 DREG[11]~173 DREG[12]~177 DREG[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.266 ns" { DREG[9] DREG[9]~165 DREG[10]~169 DREG[11]~173 DREG[12]~177 DREG[15] } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MMCLK destination 11.452 ns + Shortest register " "Info: + Shortest clock path from clock \"MMCLK\" to destination register is 11.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MMCLK 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'MMCLK'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "" { MMCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 35 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.358 ns) + CELL(0.935 ns) 5.762 ns CLK_2 2 REG LC_X3_Y14_N2 2 " "Info: 2: + IC(3.358 ns) + CELL(0.935 ns) = 5.762 ns; Loc. = LC_X3_Y14_N2; Fanout = 2; REG Node = 'CLK_2'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "4.293 ns" { MMCLK CLK_2 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 48 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.935 ns) 7.264 ns CLK_4 3 REG LC_X3_Y14_N4 2 " "Info: 3: + IC(0.567 ns) + CELL(0.935 ns) = 7.264 ns; Loc. = LC_X3_Y14_N4; Fanout = 2; REG Node = 'CLK_4'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "1.502 ns" { CLK_2 CLK_4 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 48 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.285 ns) + CELL(0.935 ns) 9.484 ns CLK_8 4 REG LC_X3_Y15_N6 20 " "Info: 4: + IC(1.285 ns) + CELL(0.935 ns) = 9.484 ns; Loc. = LC_X3_Y15_N6; Fanout = 20; REG Node = 'CLK_8'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "2.220 ns" { CLK_4 CLK_8 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 48 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.257 ns) + CELL(0.711 ns) 11.452 ns DREG\[15\] 5 REG LC_X2_Y14_N7 2 " "Info: 5: + IC(1.257 ns) + CELL(0.711 ns) = 11.452 ns; Loc. = LC_X2_Y14_N7; Fanout = 2; REG Node = 'DREG\[15\]'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "1.968 ns" { CLK_8 DREG[15] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 41 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.985 ns 43.53 % " "Info: Total cell delay = 4.985 ns ( 43.53 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.467 ns 56.47 % " "Info: Total interconnect delay = 6.467 ns ( 56.47 % )" { } { } 0} } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "11.452 ns" { MMCLK CLK_2 CLK_4 CLK_8 DREG[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.452 ns" { MMCLK MMCLK~out0 CLK_2 CLK_4 CLK_8 DREG[15] } { 0.000ns 0.000ns 3.358ns 0.567ns 1.285ns 1.257ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MMCLK source 11.452 ns - Longest register " "Info: - Longest clock path from clock \"MMCLK\" to source register is 11.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MMCLK 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'MMCLK'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "" { MMCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 35 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.358 ns) + CELL(0.935 ns) 5.762 ns CLK_2 2 REG LC_X3_Y14_N2 2 " "Info: 2: + IC(3.358 ns) + CELL(0.935 ns) = 5.762 ns; Loc. = LC_X3_Y14_N2; Fanout = 2; REG Node = 'CLK_2'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "4.293 ns" { MMCLK CLK_2 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 48 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.935 ns) 7.264 ns CLK_4 3 REG LC_X3_Y14_N4 2 " "Info: 3: + IC(0.567 ns) + CELL(0.935 ns) = 7.264 ns; Loc. = LC_X3_Y14_N4; Fanout = 2; REG Node = 'CLK_4'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "1.502 ns" { CLK_2 CLK_4 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 48 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.285 ns) + CELL(0.935 ns) 9.484 ns CLK_8 4 REG LC_X3_Y15_N6 20 " "Info: 4: + IC(1.285 ns) + CELL(0.935 ns) = 9.484 ns; Loc. = LC_X3_Y15_N6; Fanout = 20; REG Node = 'CLK_8'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "2.220 ns" { CLK_4 CLK_8 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 48 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.257 ns) + CELL(0.711 ns) 11.452 ns DREG\[9\] 5 REG LC_X2_Y14_N1 4 " "Info: 5: + IC(1.257 ns) + CELL(0.711 ns) = 11.452 ns; Loc. = LC_X2_Y14_N1; Fanout = 4; REG Node = 'DREG\[9\]'" { } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "1.968 ns" { CLK_8 DREG[9] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 41 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.985 ns 43.53 % " "Info: Total cell delay = 4.985 ns ( 43.53 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.467 ns 56.47 % " "Info: Total interconnect delay = 6.467 ns ( 56.47 % )" { } { } 0} } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "11.452 ns" { MMCLK CLK_2 CLK_4 CLK_8 DREG[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.452 ns" { MMCLK MMCLK~out0 CLK_2 CLK_4 CLK_8 DREG[9] } { 0.000ns 0.000ns 3.358ns 0.567ns 1.285ns 1.257ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } } } 0} } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "11.452 ns" { MMCLK CLK_2 CLK_4 CLK_8 DREG[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.452 ns" { MMCLK MMCLK~out0 CLK_2 CLK_4 CLK_8 DREG[15] } { 0.000ns 0.000ns 3.358ns 0.567ns 1.285ns 1.257ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "11.452 ns" { MMCLK CLK_2 CLK_4 CLK_8 DREG[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.452 ns" { MMCLK MMCLK~out0 CLK_2 CLK_4 CLK_8 DREG[9] } { 0.000ns 0.000ns 3.358ns 0.567ns 1.285ns 1.257ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 41 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 41 -1 0 } } } 0} } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "2.266 ns" { DREG[9] DREG[9]~165 DREG[10]~169 DREG[11]~173 DREG[12]~177 DREG[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.266 ns" { DREG[9] DREG[9]~165 DREG[10]~169 DREG[11]~173 DREG[12]~177 DREG[15] } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "11.452 ns" { MMCLK CLK_2 CLK_4 CLK_8 DREG[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.452 ns" { MMCLK MMCLK~out0 CLK_2 CLK_4 CLK_8 DREG[15] } { 0.000ns 0.000ns 3.358ns 0.567ns 1.285ns 1.257ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "11.452 ns" { MMCLK CLK_2 CLK_4 CLK_8 DREG[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.452 ns" { MMCLK MMCLK~out0 CLK_2 CLK_4 CLK_8 DREG[9] } { 0.000ns 0.000ns 3.358ns 0.567ns 1.285ns 1.257ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } } } 0} } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/" "" "" { DREG[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { DREG[15] } { } { } } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/FPGA代码/MYFX2.v" 41 -1 0 } } } 0}
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