op.c

QEMU 0.91 source code, supports ARM processor including S3C24xx series

{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCScheFBack[other_tc];
    FORCE_RET();
}

void op_mfc0_entrylo1 (void)
{
    T0 = (int32_t)env->CP0_EntryLo1;
    FORCE_RET();
}

void op_mfc0_context (void)
{
    T0 = (int32_t)env->CP0_Context;
    FORCE_RET();
}

void op_mfc0_pagemask (void)
{
    T0 = env->CP0_PageMask;
    FORCE_RET();
}

void op_mfc0_pagegrain (void)
{
    T0 = env->CP0_PageGrain;
    FORCE_RET();
}

void op_mfc0_wired (void)
{
    T0 = env->CP0_Wired;
    FORCE_RET();
}

void op_mfc0_srsconf0 (void)
{
    T0 = env->CP0_SRSConf0;
    FORCE_RET();
}

void op_mfc0_srsconf1 (void)
{
    T0 = env->CP0_SRSConf1;
    FORCE_RET();
}

void op_mfc0_srsconf2 (void)
{
    T0 = env->CP0_SRSConf2;
    FORCE_RET();
}

void op_mfc0_srsconf3 (void)
{
    T0 = env->CP0_SRSConf3;
    FORCE_RET();
}

void op_mfc0_srsconf4 (void)
{
    T0 = env->CP0_SRSConf4;
    FORCE_RET();
}

void op_mfc0_hwrena (void)
{
    T0 = env->CP0_HWREna;
    FORCE_RET();
}

void op_mfc0_badvaddr (void)
{
    T0 = (int32_t)env->CP0_BadVAddr;
    FORCE_RET();
}

void op_mfc0_count (void)
{
    CALL_FROM_TB0(do_mfc0_count);
    FORCE_RET();
}

void op_mfc0_entryhi (void)
{
    T0 = (int32_t)env->CP0_EntryHi;
    FORCE_RET();
}

void op_mftc0_entryhi(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
    FORCE_RET();
}

void op_mfc0_compare (void)
{
    T0 = env->CP0_Compare;
    FORCE_RET();
}

void op_mfc0_status (void)
{
    T0 = env->CP0_Status;
    FORCE_RET();
}

void op_mftc0_status(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
    uint32_t tcstatus = env->CP0_TCStatus[other_tc];

    T0 = env->CP0_Status & ~0xf1000018;
    T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
    T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
    T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
    FORCE_RET();
}

void op_mfc0_intctl (void)
{
    T0 = env->CP0_IntCtl;
    FORCE_RET();
}

void op_mfc0_srsctl (void)
{
    T0 = env->CP0_SRSCtl;
    FORCE_RET();
}

void op_mfc0_srsmap (void)
{
    T0 = env->CP0_SRSMap;
    FORCE_RET();
}

void op_mfc0_cause (void)
{
    T0 = env->CP0_Cause;
    FORCE_RET();
}

void op_mfc0_epc (void)
{
    T0 = (int32_t)env->CP0_EPC;
    FORCE_RET();
}

void op_mfc0_prid (void)
{
    T0 = env->CP0_PRid;
    FORCE_RET();
}

void op_mfc0_ebase (void)
{
    T0 = env->CP0_EBase;
    FORCE_RET();
}

void op_mfc0_config0 (void)
{
    T0 = env->CP0_Config0;
    FORCE_RET();
}

void op_mfc0_config1 (void)
{
    T0 = env->CP0_Config1;
    FORCE_RET();
}

void op_mfc0_config2 (void)
{
    T0 = env->CP0_Config2;
    FORCE_RET();
}

void op_mfc0_config3 (void)
{
    T0 = env->CP0_Config3;
    FORCE_RET();
}

void op_mfc0_config6 (void)
{
    T0 = env->CP0_Config6;
    FORCE_RET();
}

void op_mfc0_config7 (void)
{
    T0 = env->CP0_Config7;
    FORCE_RET();
}

void op_mfc0_lladdr (void)
{
    T0 = (int32_t)env->CP0_LLAddr >> 4;
    FORCE_RET();
}

void op_mfc0_watchlo (void)
{
    T0 = (int32_t)env->CP0_WatchLo[PARAM1];
    FORCE_RET();
}

void op_mfc0_watchhi (void)
{
    T0 = env->CP0_WatchHi[PARAM1];
    FORCE_RET();
}

void op_mfc0_xcontext (void)
{
    T0 = (int32_t)env->CP0_XContext;
    FORCE_RET();
}

void op_mfc0_framemask (void)
{
    T0 = env->CP0_Framemask;
    FORCE_RET();
}

void op_mfc0_debug (void)
{
    T0 = env->CP0_Debug;
    if (env->hflags & MIPS_HFLAG_DM)
        T0 |= 1 << CP0DB_DM;
    FORCE_RET();
}

void op_mftc0_debug(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    /* XXX: Might be wrong, check with EJTAG spec. */
    T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
         (env->CP0_Debug_tcstatus[other_tc] &
          ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
    FORCE_RET();
}

void op_mfc0_depc (void)
{
    T0 = (int32_t)env->CP0_DEPC;
    FORCE_RET();
}

void op_mfc0_performance0 (void)
{
    T0 = env->CP0_Performance0;
    FORCE_RET();
}

void op_mfc0_taglo (void)
{
    T0 = env->CP0_TagLo;
    FORCE_RET();
}

void op_mfc0_datalo (void)
{
    T0 = env->CP0_DataLo;
    FORCE_RET();
}

void op_mfc0_taghi (void)
{
    T0 = env->CP0_TagHi;
    FORCE_RET();
}

void op_mfc0_datahi (void)
{
    T0 = env->CP0_DataHi;
    FORCE_RET();
}

void op_mfc0_errorepc (void)
{
    T0 = (int32_t)env->CP0_ErrorEPC;
    FORCE_RET();
}

void op_mfc0_desave (void)
{
    T0 = env->CP0_DESAVE;
    FORCE_RET();
}

void op_mtc0_index (void)
{
    int num = 1;
    unsigned int tmp = env->tlb->nb_tlb;

    do {
        tmp >>= 1;
        num <<= 1;
    } while (tmp);
    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1));
    FORCE_RET();
}

void op_mtc0_mvpcontrol (void)
{
    uint32_t mask = 0;
    uint32_t newval;

    if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
        mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
                (1 << CP0MVPCo_EVP);
    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
        mask |= (1 << CP0MVPCo_STLB);
    newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask);

    // TODO: Enable/disable shared TLB, enable/disable VPEs.

    env->mvp->CP0_MVPControl = newval;
    FORCE_RET();
}

void op_mtc0_vpecontrol (void)
{
    uint32_t mask;
    uint32_t newval;

    mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
           (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
    newval = (env->CP0_VPEControl & ~mask) | (T0 & mask);

    /* Yield scheduler intercept not implemented. */
    /* Gating storage scheduler intercept not implemented. */

    // TODO: Enable/disable TCs.

    env->CP0_VPEControl = newval;
    FORCE_RET();
}

void op_mtc0_vpeconf0 (void)
{
    uint32_t mask = 0;
    uint32_t newval;

    if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
        if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
            mask |= (0xff << CP0VPEC0_XTC);
        mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
    }
    newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask);

    // TODO: TC exclusive handling due to ERL/EXL.

    env->CP0_VPEConf0 = newval;
    FORCE_RET();
}

void op_mtc0_vpeconf1 (void)
{
    uint32_t mask = 0;
    uint32_t newval;

    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
        mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
                (0xff << CP0VPEC1_NCP1);
    newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask);

    /* UDI not implemented. */
    /* CP2 not implemented. */

    // TODO: Handle FPU (CP1) binding.

    env->CP0_VPEConf1 = newval;
    FORCE_RET();
}

void op_mtc0_yqmask (void)
{
    /* Yield qualifier inputs not implemented. */
    env->CP0_YQMask = 0x00000000;
    FORCE_RET();
}

void op_mtc0_vpeschedule (void)
{
    env->CP0_VPESchedule = T0;
    FORCE_RET();
}

void op_mtc0_vpeschefback (void)
{
    env->CP0_VPEScheFBack = T0;
    FORCE_RET();
}

void op_mtc0_vpeopt (void)
{
    env->CP0_VPEOpt = T0 & 0x0000ffff;
    FORCE_RET();
}

void op_mtc0_entrylo0 (void)
{
    /* Large physaddr (PABITS) not implemented */
    /* 1k pages not implemented */
    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
    FORCE_RET();
}

void op_mtc0_tcstatus (void)
{
    uint32_t mask = env->CP0_TCStatus_rw_bitmask;
    uint32_t newval;

    newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask);

    // TODO: Sync with CP0_Status.

    env->CP0_TCStatus[env->current_tc] = newval;
    FORCE_RET();
}

void op_mttc0_tcstatus (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    // TODO: Sync with CP0_Status.

    env->CP0_TCStatus[other_tc] = T0;
    FORCE_RET();
}

void op_mtc0_tcbind (void)
{
    uint32_t mask = (1 << CP0TCBd_TBE);
    uint32_t newval;

    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
        mask |= (1 << CP0TCBd_CurVPE);
    newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask);
    env->CP0_TCBind[env->current_tc] = newval;
    FORCE_RET();
}

void op_mttc0_tcbind (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
    uint32_t mask = (1 << CP0TCBd_TBE);
    uint32_t newval;

    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
        mask |= (1 << CP0TCBd_CurVPE);
    newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask);
    env->CP0_TCBind[other_tc] = newval;
    FORCE_RET();
}

void op_mtc0_tcrestart (void)
{
    env->PC[env->current_tc] = T0;
    env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
    env->CP0_LLAddr = 0ULL;
    /* MIPS16 not implemented. */
    FORCE_RET();
}

void op_mttc0_tcrestart (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    env->PC[other_tc] = T0;
    env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
    env->CP0_LLAddr = 0ULL;
    /* MIPS16 not implemented. */
    FORCE_RET();
}

void op_mtc0_tchalt (void)
{
    env->CP0_TCHalt[env->current_tc] = T0 & 0x1;

    // TODO: Halt TC / Restart (if allocated+active) TC.

    FORCE_RET();
}

void op_mttc0_tchalt (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    // TODO: Halt TC / Restart (if allocated+active) TC.

    env->CP0_TCHalt[other_tc] = T0;
    FORCE_RET();
}

void op_mtc0_tccontext (void)
{
    env->CP0_TCContext[env->current_tc] = T0;
    FORCE_RET();
}

void op_mttc0_tccontext (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    env->CP0_TCContext[other_tc] = T0;
    FORCE_RET();
}

void op_mtc0_tcschedule (void)
{
    env->CP0_TCSchedule[env->current_tc] = T0;
    FORCE_RET();
}

void op_mttc0_tcschedule (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    env->CP0_TCSchedule[other_tc] = T0;
    FORCE_RET();
}

void op_mtc0_tcschefback (void)
{
    env->CP0_TCScheFBack[env->current_tc] = T0;
    FORCE_RET();
}

void op_mttc0_tcschefback (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    env->CP0_TCScheFBack[other_tc] = T0;
    FORCE_RET();
}

void op_mtc0_entrylo1 (void)
{
    /* Large physaddr (PABITS) not implemented */
    /* 1k pages not implemented */
    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
    FORCE_RET();
}

void op_mtc0_context (void)
{
    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
    FORCE_RET();
}

void op_mtc0_pagemask (void)
{
    /* 1k pages not implemented */
    env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
    FORCE_RET();
}

void op_mtc0_pagegrain (void)
{
    /* SmartMIPS not implemented */
    /* Large physaddr (PABITS) not implemented */
    /* 1k pages not implemented */
    env->CP0_PageGrain = 0;
    FORCE_RET();
}

void op_mtc0_wired (void)
{
    env->CP0_Wired = T0 % env->tlb->nb_tlb;
    FORCE_RET();
}

void op_mtc0_srsconf0 (void)
{
    env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask;
    FORCE_RET();
}

void op_mtc0_srsconf1 (void)
{
    env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask;
    FORCE_RET();
}

void op_mtc0_srsconf2 (void)
{
    env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask;
    FORCE_RET();
}

void op_mtc0_srsconf3 (void)
{
    env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask;
    FORCE_RET();
}

void op_mtc0_srsconf4 (void)
{
    env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask;
    FORCE_RET();
}

void op_mtc0_hwrena (void)
{
    env->CP0_HWREna = T0 & 0x0000000F;
    FORCE_RET();
}

void op_mtc0_count (void)
{
    CALL_FROM_TB2(cpu_mips_store_count, env, T0);
    FORCE_RET();
}

void op_mtc0_entryhi (void)
{
    target_ulong old, val;

    /* 1k pages not implemented */
    val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
#if defined(TARGET_MIPS64)
    val &= env->SEGMask;
#endif
    old = env->CP0_EntryHi;
    env->CP0_EntryHi = val;
    if (env->CP0_Config3 & (1 << CP0C3_MT)) {
        uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
        env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
    }
    /* If the ASID changes, flush qemu's TLB.  */
    if ((old & 0xFF) != (val & 0xFF))
        CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
    FORCE_RET();
}

void op_mttc0_entryhi(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff);
    env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff);
    FORCE_RET();
}

void op_mtc0_compare (void)
{
    CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
    FORCE_RET();
}

void op_mtc0_status (void)
{
    uint32_t val, old;
    uint32_t mask = env->CP0_Status_rw_bitmask;

    val = T0 & mask;
    old = env->CP0_Status;
    env->CP0_Status = (env->CP0_Status & ~mask) | val;