op.c

QEMU 0.91 source code, supports ARM processor including S3C24xx series

void op_dsrl (void)
{
    T0 = T0 >> T1;
    FORCE_RET();
}

void op_dsrl32 (void)
{
    T0 = T0 >> (T1 + 32);
    FORCE_RET();
}

void op_drotr (void)
{
    target_ulong tmp;

    if (T1) {
        tmp = T0 << (0x40 - T1);
        T0 = (T0 >> T1) | tmp;
    }
    FORCE_RET();
}

void op_drotr32 (void)
{
    target_ulong tmp;

    tmp = T0 << (0x40 - (32 + T1));
    T0 = (T0 >> (32 + T1)) | tmp;
    FORCE_RET();
}

void op_dsllv (void)
{
    T0 = T1 << (T0 & 0x3F);
    FORCE_RET();
}

void op_dsrav (void)
{
    T0 = (int64_t)T1 >> (T0 & 0x3F);
    FORCE_RET();
}

void op_dsrlv (void)
{
    T0 = T1 >> (T0 & 0x3F);
    FORCE_RET();
}

void op_drotrv (void)
{
    target_ulong tmp;

    T0 &= 0x3F;
    if (T0) {
        tmp = T1 << (0x40 - T0);
        T0 = (T1 >> T0) | tmp;
    } else
        T0 = T1;
    FORCE_RET();
}

void op_dclo (void)
{
    T0 = clo64(T0);
    FORCE_RET();
}

void op_dclz (void)
{
    T0 = clz64(T0);
    FORCE_RET();
}
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
#endif /* TARGET_MIPS64 */

/* 64 bits arithmetic */
#if TARGET_LONG_BITS > HOST_LONG_BITS
void op_mult (void)
{
    CALL_FROM_TB0(do_mult);
    FORCE_RET();
}

void op_multu (void)
{
    CALL_FROM_TB0(do_multu);
    FORCE_RET();
}

void op_madd (void)
{
    CALL_FROM_TB0(do_madd);
    FORCE_RET();
}

void op_maddu (void)
{
    CALL_FROM_TB0(do_maddu);
    FORCE_RET();
}

void op_msub (void)
{
    CALL_FROM_TB0(do_msub);
    FORCE_RET();
}

void op_msubu (void)
{
    CALL_FROM_TB0(do_msubu);
    FORCE_RET();
}

/* Multiplication variants of the vr54xx. */
void op_muls (void)
{
    CALL_FROM_TB0(do_muls);
    FORCE_RET();
}

void op_mulsu (void)
{
    CALL_FROM_TB0(do_mulsu);
    FORCE_RET();
}

void op_macc (void)
{
    CALL_FROM_TB0(do_macc);
    FORCE_RET();
}

void op_macchi (void)
{
    CALL_FROM_TB0(do_macchi);
    FORCE_RET();
}

void op_maccu (void)
{
    CALL_FROM_TB0(do_maccu);
    FORCE_RET();
}
void op_macchiu (void)
{
    CALL_FROM_TB0(do_macchiu);
    FORCE_RET();
}

void op_msac (void)
{
    CALL_FROM_TB0(do_msac);
    FORCE_RET();
}

void op_msachi (void)
{
    CALL_FROM_TB0(do_msachi);
    FORCE_RET();
}

void op_msacu (void)
{
    CALL_FROM_TB0(do_msacu);
    FORCE_RET();
}

void op_msachiu (void)
{
    CALL_FROM_TB0(do_msachiu);
    FORCE_RET();
}

void op_mulhi (void)
{
    CALL_FROM_TB0(do_mulhi);
    FORCE_RET();
}

void op_mulhiu (void)
{
    CALL_FROM_TB0(do_mulhiu);
    FORCE_RET();
}

void op_mulshi (void)
{
    CALL_FROM_TB0(do_mulshi);
    FORCE_RET();
}

void op_mulshiu (void)
{
    CALL_FROM_TB0(do_mulshiu);
    FORCE_RET();
}

#else /* TARGET_LONG_BITS > HOST_LONG_BITS */

static always_inline uint64_t get_HILO (void)
{
    return ((uint64_t)env->HI[0][env->current_tc] << 32) |
            ((uint64_t)(uint32_t)env->LO[0][env->current_tc]);
}

static always_inline void set_HILO (uint64_t HILO)
{
    env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF);
    env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
}

static always_inline void set_HIT0_LO (uint64_t HILO)
{
    env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF);
    T0 = env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
}

static always_inline void set_HI_LOT0 (uint64_t HILO)
{
    T0 = env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF);
    env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
}

void op_mult (void)
{
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    FORCE_RET();
}

void op_multu (void)
{
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    FORCE_RET();
}

void op_madd (void)
{
    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    set_HILO((int64_t)get_HILO() + tmp);
    FORCE_RET();
}

void op_maddu (void)
{
    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    set_HILO(get_HILO() + tmp);
    FORCE_RET();
}

void op_msub (void)
{
    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    set_HILO((int64_t)get_HILO() - tmp);
    FORCE_RET();
}

void op_msubu (void)
{
    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    set_HILO(get_HILO() - tmp);
    FORCE_RET();
}

/* Multiplication variants of the vr54xx. */
void op_muls (void)
{
    set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
    FORCE_RET();
}

void op_mulsu (void)
{
    set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
    FORCE_RET();
}

void op_macc (void)
{
    set_HI_LOT0(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
    FORCE_RET();
}

void op_macchi (void)
{
    set_HIT0_LO(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
    FORCE_RET();
}

void op_maccu (void)
{
    set_HI_LOT0(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
    FORCE_RET();
}

void op_macchiu (void)
{
    set_HIT0_LO(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
    FORCE_RET();
}

void op_msac (void)
{
    set_HI_LOT0(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
    FORCE_RET();
}

void op_msachi (void)
{
    set_HIT0_LO(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
    FORCE_RET();
}

void op_msacu (void)
{
    set_HI_LOT0(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
    FORCE_RET();
}

void op_msachiu (void)
{
    set_HIT0_LO(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
    FORCE_RET();
}

void op_mulhi (void)
{
    set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    FORCE_RET();
}

void op_mulhiu (void)
{
    set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    FORCE_RET();
}

void op_mulshi (void)
{
    set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
    FORCE_RET();
}

void op_mulshiu (void)
{
    set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
    FORCE_RET();
}

#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */

#if defined(TARGET_MIPS64)
void op_dmult (void)
{
    CALL_FROM_TB4(muls64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
    FORCE_RET();
}

void op_dmultu (void)
{
    CALL_FROM_TB4(mulu64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
    FORCE_RET();
}
#endif

/* Conditional moves */
void op_movn (void)
{
    if (T1 != 0)
        env->gpr[PARAM1][env->current_tc] = T0;
    FORCE_RET();
}

void op_movz (void)
{
    if (T1 == 0)
        env->gpr[PARAM1][env->current_tc] = T0;
    FORCE_RET();
}

void op_movf (void)
{
    if (!(env->fpu->fcr31 & PARAM1))
        T0 = T1;
    FORCE_RET();
}

void op_movt (void)
{
    if (env->fpu->fcr31 & PARAM1)
        T0 = T1;
    FORCE_RET();
}

/* Tests */
#define OP_COND(name, cond) \
void glue(op_, name) (void) \
{                           \
    if (cond) {             \
        T0 = 1;             \
    } else {                \
        T0 = 0;             \
    }                       \
    FORCE_RET();            \
}

OP_COND(eq, T0 == T1);
OP_COND(ne, T0 != T1);
OP_COND(ge, (target_long)T0 >= (target_long)T1);
OP_COND(geu, T0 >= T1);
OP_COND(lt, (target_long)T0 < (target_long)T1);
OP_COND(ltu, T0 < T1);
OP_COND(gez, (target_long)T0 >= 0);
OP_COND(gtz, (target_long)T0 > 0);
OP_COND(lez, (target_long)T0 <= 0);
OP_COND(ltz, (target_long)T0 < 0);

/* Branches */
void OPPROTO op_goto_tb0(void)
{
    GOTO_TB(op_goto_tb0, PARAM1, 0);
    FORCE_RET();
}

void OPPROTO op_goto_tb1(void)
{
    GOTO_TB(op_goto_tb1, PARAM1, 1);
    FORCE_RET();
}

/* Branch to register */
void op_save_breg_target (void)
{
    env->btarget = T2;
    FORCE_RET();
}

void op_restore_breg_target (void)
{
    T2 = env->btarget;
    FORCE_RET();
}

void op_breg (void)
{
    env->PC[env->current_tc] = T2;
    FORCE_RET();
}

void op_save_btarget (void)
{
    env->btarget = PARAM1;
    FORCE_RET();
}

#if defined(TARGET_MIPS64)
void op_save_btarget64 (void)
{
    env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
    FORCE_RET();
}
#endif

/* Conditional branch */
void op_set_bcond (void)
{
    T2 = T0;
    FORCE_RET();
}

void op_save_bcond (void)
{
    env->bcond = T2;
    FORCE_RET();
}

void op_restore_bcond (void)
{
    T2 = env->bcond;
    FORCE_RET();
}

void op_jnz_T2 (void)
{
    if (T2)
        GOTO_LABEL_PARAM(1);
    FORCE_RET();
}

/* CP0 functions */
void op_mfc0_index (void)
{
    T0 = env->CP0_Index;
    FORCE_RET();
}

void op_mfc0_mvpcontrol (void)
{
    T0 = env->mvp->CP0_MVPControl;
    FORCE_RET();
}

void op_mfc0_mvpconf0 (void)
{
    T0 = env->mvp->CP0_MVPConf0;
    FORCE_RET();
}

void op_mfc0_mvpconf1 (void)
{
    T0 = env->mvp->CP0_MVPConf1;
    FORCE_RET();
}

void op_mfc0_random (void)
{
    CALL_FROM_TB0(do_mfc0_random);
    FORCE_RET();
}

void op_mfc0_vpecontrol (void)
{
    T0 = env->CP0_VPEControl;
    FORCE_RET();
}

void op_mfc0_vpeconf0 (void)
{
    T0 = env->CP0_VPEConf0;
    FORCE_RET();
}

void op_mfc0_vpeconf1 (void)
{
    T0 = env->CP0_VPEConf1;
    FORCE_RET();
}

void op_mfc0_yqmask (void)
{
    T0 = env->CP0_YQMask;
    FORCE_RET();
}

void op_mfc0_vpeschedule (void)
{
    T0 = env->CP0_VPESchedule;
    FORCE_RET();
}

void op_mfc0_vpeschefback (void)
{
    T0 = env->CP0_VPEScheFBack;
    FORCE_RET();
}

void op_mfc0_vpeopt (void)
{
    T0 = env->CP0_VPEOpt;
    FORCE_RET();
}

void op_mfc0_entrylo0 (void)
{
    T0 = (int32_t)env->CP0_EntryLo0;
    FORCE_RET();
}

void op_mfc0_tcstatus (void)
{
    T0 = env->CP0_TCStatus[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tcstatus(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCStatus[other_tc];
    FORCE_RET();
}

void op_mfc0_tcbind (void)
{
    T0 = env->CP0_TCBind[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tcbind(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCBind[other_tc];
    FORCE_RET();
}

void op_mfc0_tcrestart (void)
{
    T0 = env->PC[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tcrestart(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->PC[other_tc];
    FORCE_RET();
}

void op_mfc0_tchalt (void)
{
    T0 = env->CP0_TCHalt[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tchalt(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCHalt[other_tc];
    FORCE_RET();
}

void op_mfc0_tccontext (void)
{
    T0 = env->CP0_TCContext[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tccontext(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCContext[other_tc];
    FORCE_RET();
}

void op_mfc0_tcschedule (void)
{
    T0 = env->CP0_TCSchedule[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tcschedule(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCSchedule[other_tc];
    FORCE_RET();
}

void op_mfc0_tcschefback (void)
{
    T0 = env->CP0_TCScheFBack[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tcschefback(void)