sh7750_regs.h

QEMU 0.91 source code, supports ARM processor including S3C24xx series

#define SH7750_DMATCR1_P4     SH7750_DMATCR(1)
#define SH7750_DMATCR2_P4     SH7750_DMATCR(2)
#define SH7750_DMATCR3_P4     SH7750_DMATCR(3)
#define SH7750_DMATCR0_A7     SH7750_DMATCR_A7(0)
#define SH7750_DMATCR1_A7     SH7750_DMATCR_A7(1)
#define SH7750_DMATCR2_A7     SH7750_DMATCR_A7(2)
#define SH7750_DMATCR3_A7     SH7750_DMATCR_A7(3)

/* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */
#define SH7750_CHCR_REGOFS(n)  (0xA0000C + ((n)*16))	/* offset */
#define SH7750_CHCR(n)        SH7750_P4_REG32(SH7750_CHCR_REGOFS(n))
#define SH7750_CHCR_A7(n)     SH7750_A7_REG32(SH7750_CHCR_REGOFS(n))
#define SH7750_CHCR0          SH7750_CHCR(0)
#define SH7750_CHCR1          SH7750_CHCR(1)
#define SH7750_CHCR2          SH7750_CHCR(2)
#define SH7750_CHCR3          SH7750_CHCR(3)
#define SH7750_CHCR0_A7       SH7750_CHCR_A7(0)
#define SH7750_CHCR1_A7       SH7750_CHCR_A7(1)
#define SH7750_CHCR2_A7       SH7750_CHCR_A7(2)
#define SH7750_CHCR3_A7       SH7750_CHCR_A7(3)

#define SH7750_CHCR_SSA       0xE0000000	/* Source Address Space Attribute */
#define SH7750_CHCR_SSA_PCMCIA  0x00000000	/* Reserved in PCMCIA access */
#define SH7750_CHCR_SSA_DYNBSZ  0x20000000	/* Dynamic Bus Sizing I/O space */
#define SH7750_CHCR_SSA_IO8     0x40000000	/* 8-bit I/O space */
#define SH7750_CHCR_SSA_IO16    0x60000000	/* 16-bit I/O space */
#define SH7750_CHCR_SSA_CMEM8   0x80000000	/* 8-bit common memory space */
#define SH7750_CHCR_SSA_CMEM16  0xA0000000	/* 16-bit common memory space */
#define SH7750_CHCR_SSA_AMEM8   0xC0000000	/* 8-bit attribute memory space */
#define SH7750_CHCR_SSA_AMEM16  0xE0000000	/* 16-bit attribute memory space */

#define SH7750_CHCR_STC       0x10000000	/* Source Address Wait Control Select,
						   specifies CS5 or CS6 space wait
						   control for PCMCIA access */

#define SH7750_CHCR_DSA       0x0E000000	/* Source Address Space Attribute */
#define SH7750_CHCR_DSA_PCMCIA  0x00000000	/* Reserved in PCMCIA access */
#define SH7750_CHCR_DSA_DYNBSZ  0x02000000	/* Dynamic Bus Sizing I/O space */
#define SH7750_CHCR_DSA_IO8     0x04000000	/* 8-bit I/O space */
#define SH7750_CHCR_DSA_IO16    0x06000000	/* 16-bit I/O space */
#define SH7750_CHCR_DSA_CMEM8   0x08000000	/* 8-bit common memory space */
#define SH7750_CHCR_DSA_CMEM16  0x0A000000	/* 16-bit common memory space */
#define SH7750_CHCR_DSA_AMEM8   0x0C000000	/* 8-bit attribute memory space */
#define SH7750_CHCR_DSA_AMEM16  0x0E000000	/* 16-bit attribute memory space */

#define SH7750_CHCR_DTC       0x01000000	/* Destination Address Wait Control
						   Select, specifies CS5 or CS6
						   space wait control for PCMCIA
						   access */

#define SH7750_CHCR_DS        0x00080000	/* DREQ\ Select : */
#define SH7750_CHCR_DS_LOWLVL 0x00000000	/*     Low Level Detection */
#define SH7750_CHCR_DS_FALL   0x00080000	/*     Falling Edge Detection */

#define SH7750_CHCR_RL        0x00040000	/* Request Check Level: */
#define SH7750_CHCR_RL_ACTH   0x00000000	/*     DRAK is an active high out */
#define SH7750_CHCR_RL_ACTL   0x00040000	/*     DRAK is an active low out */

#define SH7750_CHCR_AM        0x00020000	/* Acknowledge Mode: */
#define SH7750_CHCR_AM_RD     0x00000000	/*     DACK is output in read cycle */
#define SH7750_CHCR_AM_WR     0x00020000	/*     DACK is output in write cycle */

#define SH7750_CHCR_AL        0x00010000	/* Acknowledge Level: */
#define SH7750_CHCR_AL_ACTH   0x00000000	/*     DACK is an active high out */
#define SH7750_CHCR_AL_ACTL   0x00010000	/*     DACK is an active low out */

#define SH7750_CHCR_DM        0x0000C000	/* Destination Address Mode: */
#define SH7750_CHCR_DM_FIX    0x00000000	/*     Destination Addr Fixed */
#define SH7750_CHCR_DM_INC    0x00004000	/*     Destination Addr Incremented */
#define SH7750_CHCR_DM_DEC    0x00008000	/*     Destination Addr Decremented */

#define SH7750_CHCR_SM        0x00003000	/* Source Address Mode: */
#define SH7750_CHCR_SM_FIX    0x00000000	/*     Source Addr Fixed */
#define SH7750_CHCR_SM_INC    0x00001000	/*     Source Addr Incremented */
#define SH7750_CHCR_SM_DEC    0x00002000	/*     Source Addr Decremented */

#define SH7750_CHCR_RS        0x00000F00	/* Request Source Select: */
#define SH7750_CHCR_RS_ER_DA_EA_TO_EA   0x000	/* External Request, Dual Address
						   Mode (External Addr Space->
						   External Addr Space) */
#define SH7750_CHCR_RS_ER_SA_EA_TO_ED   0x200	/* External Request, Single
						   Address Mode (External Addr
						   Space -> External Device) */
#define SH7750_CHCR_RS_ER_SA_ED_TO_EA   0x300	/* External Request, Single
						   Address Mode, (External
						   Device -> External Addr
						   Space) */
#define SH7750_CHCR_RS_AR_EA_TO_EA      0x400	/* Auto-Request (External Addr
						   Space -> External Addr Space) */

#define SH7750_CHCR_RS_AR_EA_TO_OCP     0x500	/* Auto-Request (External Addr
						   Space -> On-chip Peripheral
						   Module) */
#define SH7750_CHCR_RS_AR_OCP_TO_EA     0x600	/* Auto-Request (On-chip
						   Peripheral Module ->
						   External Addr Space */
#define SH7750_CHCR_RS_SCITX_EA_TO_SC   0x800	/* SCI Transmit-Data-Empty intr
						   transfer request (external
						   address space -> SCTDR1) */
#define SH7750_CHCR_RS_SCIRX_SC_TO_EA   0x900	/* SCI Receive-Data-Full intr
						   transfer request (SCRDR1 ->
						   External Addr Space) */
#define SH7750_CHCR_RS_SCIFTX_EA_TO_SC  0xA00	/* SCIF Transmit-Data-Empty intr
						   transfer request (external
						   address space -> SCFTDR1) */
#define SH7750_CHCR_RS_SCIFRX_SC_TO_EA  0xB00	/* SCIF Receive-Data-Full intr
						   transfer request (SCFRDR2 ->
						   External Addr Space) */
#define SH7750_CHCR_RS_TMU2_EA_TO_EA    0xC00	/* TMU Channel 2 (input capture
						   interrupt), (external address
						   space -> external address
						   space) */
#define SH7750_CHCR_RS_TMU2_EA_TO_OCP   0xD00	/* TMU Channel 2 (input capture
						   interrupt), (external address
						   space -> on-chip peripheral
						   module) */
#define SH7750_CHCR_RS_TMU2_OCP_TO_EA   0xE00	/* TMU Channel 2 (input capture
						   interrupt), (on-chip
						   peripheral module -> external
						   address space) */

#define SH7750_CHCR_TM        0x00000080	/* Transmit mode: */
#define SH7750_CHCR_TM_CSTEAL 0x00000000	/*     Cycle Steal Mode */
#define SH7750_CHCR_TM_BURST  0x00000080	/*     Burst Mode */

#define SH7750_CHCR_TS        0x00000070	/* Transmit Size: */
#define SH7750_CHCR_TS_QUAD   0x00000000	/*     Quadword Size (64 bits) */
#define SH7750_CHCR_TS_BYTE   0x00000010	/*     Byte Size (8 bit) */
#define SH7750_CHCR_TS_WORD   0x00000020	/*     Word Size (16 bit) */
#define SH7750_CHCR_TS_LONG   0x00000030	/*     Longword Size (32 bit) */
#define SH7750_CHCR_TS_BLOCK  0x00000040	/*     32-byte block transfer */

#define SH7750_CHCR_IE        0x00000004	/* Interrupt Enable */
#define SH7750_CHCR_TE        0x00000002	/* Transfer End */
#define SH7750_CHCR_DE        0x00000001	/* DMAC Enable */

/* DMA Operation Register - DMAOR */
#define SH7750_DMAOR_REGOFS   0xA00040	/* offset */
#define SH7750_DMAOR          SH7750_P4_REG32(SH7750_DMAOR_REGOFS)
#define SH7750_DMAOR_A7       SH7750_A7_REG32(SH7750_DMAOR_REGOFS)

#define SH7750_DMAOR_DDT      0x00008000	/* On-Demand Data Transfer Mode */

#define SH7750_DMAOR_PR       0x00000300	/* Priority Mode: */
#define SH7750_DMAOR_PR_0123  0x00000000	/*     CH0 > CH1 > CH2 > CH3 */
#define SH7750_DMAOR_PR_0231  0x00000100	/*     CH0 > CH2 > CH3 > CH1 */
#define SH7750_DMAOR_PR_2013  0x00000200	/*     CH2 > CH0 > CH1 > CH3 */
#define SH7750_DMAOR_PR_RR    0x00000300	/*     Round-robin mode */

#define SH7750_DMAOR_COD      0x00000010	/* Check Overrun for DREQ\ */
#define SH7750_DMAOR_AE       0x00000004	/* Address Error flag */
#define SH7750_DMAOR_NMIF     0x00000002	/* NMI Flag */
#define SH7750_DMAOR_DME      0x00000001	/* DMAC Master Enable */

/*
 * I/O Ports
 */
/* Port Control Register A - PCTRA */
#define SH7750_PCTRA_REGOFS   0x80002C	/* offset */
#define SH7750_PCTRA          SH7750_P4_REG32(SH7750_PCTRA_REGOFS)
#define SH7750_PCTRA_A7       SH7750_A7_REG32(SH7750_PCTRA_REGOFS)

#define SH7750_PCTRA_PBPUP(n) 0	/* Bit n is pulled up */
#define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1))	/* Bit n is not pulled up */
#define SH7750_PCTRA_PBINP(n) 0	/* Bit n is an input */
#define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2))	/* Bit n is an output */

/* Port Data Register A - PDTRA(half) */
#define SH7750_PDTRA_REGOFS   0x800030	/* offset */
#define SH7750_PDTRA          SH7750_P4_REG32(SH7750_PDTRA_REGOFS)
#define SH7750_PDTRA_A7       SH7750_A7_REG32(SH7750_PDTRA_REGOFS)

#define SH7750_PDTRA_BIT(n) (1 << (n))

/* Port Control Register B - PCTRB */
#define SH7750_PCTRB_REGOFS   0x800040	/* offset */
#define SH7750_PCTRB          SH7750_P4_REG32(SH7750_PCTRB_REGOFS)
#define SH7750_PCTRB_A7       SH7750_A7_REG32(SH7750_PCTRB_REGOFS)

#define SH7750_PCTRB_PBPUP(n) 0	/* Bit n is pulled up */
#define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1))	/* Bit n is not pulled up */
#define SH7750_PCTRB_PBINP(n) 0	/* Bit n is an input */
#define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2))	/* Bit n is an output */

/* Port Data Register B - PDTRB(half) */
#define SH7750_PDTRB_REGOFS   0x800044	/* offset */
#define SH7750_PDTRB          SH7750_P4_REG32(SH7750_PDTRB_REGOFS)
#define SH7750_PDTRB_A7       SH7750_A7_REG32(SH7750_PDTRB_REGOFS)

#define SH7750_PDTRB_BIT(n) (1 << ((n)-16))

/* GPIO Interrupt Control Register - GPIOIC(half) */
#define SH7750_GPIOIC_REGOFS  0x800048	/* offset */
#define SH7750_GPIOIC         SH7750_P4_REG32(SH7750_GPIOIC_REGOFS)
#define SH7750_GPIOIC_A7      SH7750_A7_REG32(SH7750_GPIOIC_REGOFS)

#define SH7750_GPIOIC_PTIREN(n) (1 << (n))	/* Port n is used as a GPIO int */

/*
 * Interrupt Controller - INTC
 */
/* Interrupt Control Register - ICR (half) */
#define SH7750_ICR_REGOFS     0xD00000	/* offset */
#define SH7750_ICR            SH7750_P4_REG32(SH7750_ICR_REGOFS)
#define SH7750_ICR_A7         SH7750_A7_REG32(SH7750_ICR_REGOFS)

#define SH7750_ICR_NMIL       0x8000	/* NMI Input Level */
#define SH7750_ICR_MAI        0x4000	/* NMI Interrupt Mask */

#define SH7750_ICR_NMIB       0x0200	/* NMI Block Mode: */
#define SH7750_ICR_NMIB_BLK   0x0000	/*   NMI requests held pending while
					   SR.BL bit is set to 1 */
#define SH7750_ICR_NMIB_NBLK  0x0200	/*   NMI requests detected when SR.BL bit
					   set to 1 */

#define SH7750_ICR_NMIE       0x0100	/* NMI Edge Select: */
#define SH7750_ICR_NMIE_FALL  0x0000	/*   Interrupt request detected on falling
					   edge of NMI input */
#define SH7750_ICR_NMIE_RISE  0x0100	/*   Interrupt request detected on rising
					   edge of NMI input */

#define SH7750_ICR_IRLM       0x0080	/* IRL Pin Mode: */
#define SH7750_ICR_IRLM_ENC   0x0000	/*   IRL\ pins used as a level-encoded
					   interrupt requests */
#define SH7750_ICR_IRLM_RAW   0x0080	/*   IRL\ pins used as a four independent
					   interrupt requests */

/*
 * User Break Controller registers
 */
#define SH7750_BARA           0x200000	/* Break address regiser A */
#define SH7750_BAMRA          0x200004	/* Break address mask regiser A */
#define SH7750_BBRA           0x200008	/* Break bus cycle regiser A */
#define SH7750_BARB           0x20000c	/* Break address regiser B */
#define SH7750_BAMRB          0x200010	/* Break address mask regiser B */
#define SH7750_BBRB           0x200014	/* Break bus cycle regiser B */
#define SH7750_BASRB          0x000018	/* Break ASID regiser B */
#define SH7750_BDRB           0x200018	/* Break data regiser B */
#define SH7750_BDMRB          0x20001c	/* Break data mask regiser B */
#define SH7750_BRCR           0x200020	/* Break control register */

#define SH7750_BRCR_UDBE        0x0001	/* User break debug enable bit */

/*
 * Missing in RTEMS, added for QEMU
 */
#define SH7750_BCR3_A7       0x1f800050
#define SH7750_BCR4_A7       0x1e0a00f0
#define SH7750_PRECHARGE0_A7 0x1f900088
#define SH7750_PRECHARGE1_A7 0x1f940088

#endif