sh7750_regs.h

QEMU 0.91 source code, supports ARM processor including S3C24xx series

#define SH7750_RCR2_A7        SH7750_A7_REG32(SH7750_RCR2_REGOFS)
#define SH7750_RCR2_PEF        0x80	/* Periodic Interrupt Flag */
#define SH7750_RCR2_PES        0x70	/* Periodic Interrupt Enable: */
#define SH7750_RCR2_PES_DIS    0x00	/*   Periodic Interrupt Disabled */
#define SH7750_RCR2_PES_DIV256 0x10	/*   Generated at 1/256 sec interval */
#define SH7750_RCR2_PES_DIV64  0x20	/*   Generated at 1/64 sec interval */
#define SH7750_RCR2_PES_DIV16  0x30	/*   Generated at 1/16 sec interval */
#define SH7750_RCR2_PES_DIV4   0x40	/*   Generated at 1/4 sec interval */
#define SH7750_RCR2_PES_DIV2   0x50	/*   Generated at 1/2 sec interval */
#define SH7750_RCR2_PES_x1     0x60	/*   Generated at 1 sec interval */
#define SH7750_RCR2_PES_x2     0x70	/*   Generated at 2 sec interval */
#define SH7750_RCR2_RTCEN      0x08	/* RTC Crystal Oscillator is Operated */
#define SH7750_RCR2_ADJ        0x04	/* 30-Second Adjastment */
#define SH7750_RCR2_RESET      0x02	/* Frequency divider circuits are reset */
#define SH7750_RCR2_START      0x01	/* 0 - sec, min, hr, day-of-week, month,
					   year counters are stopped
					   1 - sec, min, hr, day-of-week, month,
					   year counters operate normally */
/*
 * Bus State Controller - BSC
 */
/* Bus Control Register 1 - BCR1 */
#define SH7750_BCR1_REGOFS    0x800000	/* offset */
#define SH7750_BCR1           SH7750_P4_REG32(SH7750_BCR1_REGOFS)
#define SH7750_BCR1_A7        SH7750_A7_REG32(SH7750_BCR1_REGOFS)
#define SH7750_BCR1_ENDIAN    0x80000000	/* Endianness (1 - little endian) */
#define SH7750_BCR1_MASTER    0x40000000	/* Master/Slave mode (1-master) */
#define SH7750_BCR1_A0MPX     0x20000000	/* Area 0 Memory Type (0-SRAM,1-MPX) */
#define SH7750_BCR1_IPUP      0x02000000	/* Input Pin Pull-up Control:
						   0 - pull-up resistor is on for
						   control input pins
						   1 - pull-up resistor is off */
#define SH7750_BCR1_OPUP      0x01000000	/* Output Pin Pull-up Control:
						   0 - pull-up resistor is on for
						   control output pins
						   1 - pull-up resistor is off */
#define SH7750_BCR1_A1MBC     0x00200000	/* Area 1 SRAM Byte Control Mode:
						   0 - Area 1 SRAM is set to
						   normal mode
						   1 - Area 1 SRAM is set to byte
						   control mode */
#define SH7750_BCR1_A4MBC     0x00100000	/* Area 4 SRAM Byte Control Mode:
						   0 - Area 4 SRAM is set to
						   normal mode
						   1 - Area 4 SRAM is set to byte
						   control mode */
#define SH7750_BCR1_BREQEN    0x00080000	/* BREQ Enable:
						   0 - External requests are  not
						   accepted
						   1 - External requests are
						   accepted */
#define SH7750_BCR1_PSHR      0x00040000	/* Partial Sharing Bit:
						   0 - Master Mode
						   1 - Partial-sharing Mode */
#define SH7750_BCR1_MEMMPX    0x00020000	/* Area 1 to 6 MPX Interface:
						   0 - SRAM/burst ROM interface
						   1 - MPX interface */
#define SH7750_BCR1_HIZMEM    0x00008000	/* High Impendance Control. Specifies
						   the state of A[25:0], BS\, CSn\,
						   RD/WR\, CE2A\, CE2B\ in standby
						   mode and when bus is released:
						   0 - signals go to High-Z mode
						   1 - signals driven */
#define SH7750_BCR1_HIZCNT    0x00004000	/* High Impendance Control. Specifies
						   the state of the RAS\, RAS2\, WEn\,
						   CASn\, DQMn, RD\, CASS\, FRAME\,
						   RD2\ signals in standby mode and
						   when bus is released:
						   0 - signals go to High-Z mode
						   1 - signals driven */
#define SH7750_BCR1_A0BST     0x00003800	/* Area 0 Burst ROM Control */
#define SH7750_BCR1_A0BST_SRAM    0x0000	/*   Area 0 accessed as SRAM i/f */
#define SH7750_BCR1_A0BST_ROM4    0x0800	/*   Area 0 accessed as burst ROM
						   interface, 4 cosequtive access */
#define SH7750_BCR1_A0BST_ROM8    0x1000	/*   Area 0 accessed as burst ROM
						   interface, 8 cosequtive access */
#define SH7750_BCR1_A0BST_ROM16   0x1800	/*   Area 0 accessed as burst ROM
						   interface, 16 cosequtive access */
#define SH7750_BCR1_A0BST_ROM32   0x2000	/*   Area 0 accessed as burst ROM
						   interface, 32 cosequtive access */

#define SH7750_BCR1_A5BST     0x00000700	/* Area 5 Burst ROM Control */
#define SH7750_BCR1_A5BST_SRAM    0x0000	/*   Area 5 accessed as SRAM i/f */
#define SH7750_BCR1_A5BST_ROM4    0x0100	/*   Area 5 accessed as burst ROM
						   interface, 4 cosequtive access */
#define SH7750_BCR1_A5BST_ROM8    0x0200	/*   Area 5 accessed as burst ROM
						   interface, 8 cosequtive access */
#define SH7750_BCR1_A5BST_ROM16   0x0300	/*   Area 5 accessed as burst ROM
						   interface, 16 cosequtive access */
#define SH7750_BCR1_A5BST_ROM32   0x0400	/*   Area 5 accessed as burst ROM
						   interface, 32 cosequtive access */

#define SH7750_BCR1_A6BST     0x000000E0	/* Area 6 Burst ROM Control */
#define SH7750_BCR1_A6BST_SRAM    0x0000	/*   Area 6 accessed as SRAM i/f */
#define SH7750_BCR1_A6BST_ROM4    0x0020	/*   Area 6 accessed as burst ROM
						   interface, 4 cosequtive access */
#define SH7750_BCR1_A6BST_ROM8    0x0040	/*   Area 6 accessed as burst ROM
						   interface, 8 cosequtive access */
#define SH7750_BCR1_A6BST_ROM16   0x0060	/*   Area 6 accessed as burst ROM
						   interface, 16 cosequtive access */
#define SH7750_BCR1_A6BST_ROM32   0x0080	/*   Area 6 accessed as burst ROM
						   interface, 32 cosequtive access */

#define SH7750_BCR1_DRAMTP        0x001C	/* Area 2 and 3 Memory Type */
#define SH7750_BCR1_DRAMTP_2SRAM_3SRAM   0x0000	/* Area 2 and 3 are SRAM or MPX
						   interface. */
#define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM  0x0008	/* Area 2 - SRAM/MPX, Area 3 -
						   synchronous DRAM */
#define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C	/* Area 2 and 3 are synchronous
						   DRAM interface */
#define SH7750_BCR1_DRAMTP_2SRAM_3DRAM   0x0010	/* Area 2 - SRAM/MPX, Area 3 -
						   DRAM interface */
#define SH7750_BCR1_DRAMTP_2DRAM_3DRAM   0x0014	/* Area 2 and 3 are DRAM
						   interface */

#define SH7750_BCR1_A56PCM    0x00000001	/* Area 5 and 6 Bus Type:
						   0 - SRAM interface
						   1 - PCMCIA interface */

/* Bus Control Register 2 (half) - BCR2 */
#define SH7750_BCR2_REGOFS    0x800004	/* offset */
#define SH7750_BCR2           SH7750_P4_REG32(SH7750_BCR2_REGOFS)
#define SH7750_BCR2_A7        SH7750_A7_REG32(SH7750_BCR2_REGOFS)

#define SH7750_BCR2_A0SZ      0xC000	/* Area 0 Bus Width */
#define SH7750_BCR2_A0SZ_S    14
#define SH7750_BCR2_A6SZ      0x3000	/* Area 6 Bus Width */
#define SH7750_BCR2_A6SZ_S    12
#define SH7750_BCR2_A5SZ      0x0C00	/* Area 5 Bus Width */
#define SH7750_BCR2_A5SZ_S    10
#define SH7750_BCR2_A4SZ      0x0300	/* Area 4 Bus Width */
#define SH7750_BCR2_A4SZ_S    8
#define SH7750_BCR2_A3SZ      0x00C0	/* Area 3 Bus Width */
#define SH7750_BCR2_A3SZ_S    6
#define SH7750_BCR2_A2SZ      0x0030	/* Area 2 Bus Width */
#define SH7750_BCR2_A2SZ_S    4
#define SH7750_BCR2_A1SZ      0x000C	/* Area 1 Bus Width */
#define SH7750_BCR2_A1SZ_S    2
#define SH7750_BCR2_SZ_64     0	/* 64 bits */
#define SH7750_BCR2_SZ_8      1	/* 8 bits */
#define SH7750_BCR2_SZ_16     2	/* 16 bits */
#define SH7750_BCR2_SZ_32     3	/* 32 bits */
#define SH7750_BCR2_PORTEN    0x0001	/* Port Function Enable :
					   0 - D51-D32 are not used as a port
					   1 - D51-D32 are used as a port */

/* Wait Control Register 1 - WCR1 */
#define SH7750_WCR1_REGOFS    0x800008	/* offset */
#define SH7750_WCR1           SH7750_P4_REG32(SH7750_WCR1_REGOFS)
#define SH7750_WCR1_A7        SH7750_A7_REG32(SH7750_WCR1_REGOFS)
#define SH7750_WCR1_DMAIW     0x70000000	/* DACK Device Inter-Cycle Idle
						   specification */
#define SH7750_WCR1_DMAIW_S   28
#define SH7750_WCR1_A6IW      0x07000000	/* Area 6 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A6IW_S    24
#define SH7750_WCR1_A5IW      0x00700000	/* Area 5 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A5IW_S    20
#define SH7750_WCR1_A4IW      0x00070000	/* Area 4 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A4IW_S    16
#define SH7750_WCR1_A3IW      0x00007000	/* Area 3 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A3IW_S    12
#define SH7750_WCR1_A2IW      0x00000700	/* Area 2 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A2IW_S    8
#define SH7750_WCR1_A1IW      0x00000070	/* Area 1 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A1IW_S    4
#define SH7750_WCR1_A0IW      0x00000007	/* Area 0 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A0IW_S    0

/* Wait Control Register 2 - WCR2 */
#define SH7750_WCR2_REGOFS    0x80000C	/* offset */
#define SH7750_WCR2           SH7750_P4_REG32(SH7750_WCR2_REGOFS)
#define SH7750_WCR2_A7        SH7750_A7_REG32(SH7750_WCR2_REGOFS)

#define SH7750_WCR2_A6W       0xE0000000	/* Area 6 Wait Control */
#define SH7750_WCR2_A6W_S     29
#define SH7750_WCR2_A6B       0x1C000000	/* Area 6 Burst Pitch */
#define SH7750_WCR2_A6B_S     26
#define SH7750_WCR2_A5W       0x03800000	/* Area 5 Wait Control */
#define SH7750_WCR2_A5W_S     23
#define SH7750_WCR2_A5B       0x00700000	/* Area 5 Burst Pitch */
#define SH7750_WCR2_A5B_S     20
#define SH7750_WCR2_A4W       0x000E0000	/* Area 4 Wait Control */
#define SH7750_WCR2_A4W_S     17
#define SH7750_WCR2_A3W       0x0000E000	/* Area 3 Wait Control */
#define SH7750_WCR2_A3W_S     13
#define SH7750_WCR2_A2W       0x00000E00	/* Area 2 Wait Control */
#define SH7750_WCR2_A2W_S     9
#define SH7750_WCR2_A1W       0x000001C0	/* Area 1 Wait Control */
#define SH7750_WCR2_A1W_S     6
#define SH7750_WCR2_A0W       0x00000038	/* Area 0 Wait Control */
#define SH7750_WCR2_A0W_S     3
#define SH7750_WCR2_A0B       0x00000007	/* Area 0 Burst Pitch */
#define SH7750_WCR2_A0B_S     0

#define SH7750_WCR2_WS0       0	/* 0 wait states inserted */
#define SH7750_WCR2_WS1       1	/* 1 wait states inserted */
#define SH7750_WCR2_WS2       2	/* 2 wait states inserted */
#define SH7750_WCR2_WS3       3	/* 3 wait states inserted */
#define SH7750_WCR2_WS6       4	/* 6 wait states inserted */
#define SH7750_WCR2_WS9       5	/* 9 wait states inserted */
#define SH7750_WCR2_WS12      6	/* 12 wait states inserted */
#define SH7750_WCR2_WS15      7	/* 15 wait states inserted */

#define SH7750_WCR2_BPWS0     0	/* 0 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS1     1	/* 1 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS2     2	/* 2 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS3     3	/* 3 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS4     4	/* 4 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS5     5	/* 5 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS6     6	/* 6 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS7     7	/* 7 wait states inserted from 2nd access */

/* DRAM CAS\ Assertion Delay (area 3,2) */
#define SH7750_WCR2_DRAM_CAS_ASW1   0	/* 1 cycle */
#define SH7750_WCR2_DRAM_CAS_ASW2   1	/* 2 cycles */
#define SH7750_WCR2_DRAM_CAS_ASW3   2	/* 3 cycles */
#define SH7750_WCR2_DRAM_CAS_ASW4   3	/* 4 cycles */
#define SH7750_WCR2_DRAM_CAS_ASW7   4	/* 7 cycles */
#define SH7750_WCR2_DRAM_CAS_ASW10  5	/* 10 cycles */
#define SH7750_WCR2_DRAM_CAS_ASW13  6	/* 13 cycles */
#define SH7750_WCR2_DRAM_CAS_ASW16  7	/* 16 cycles */

/* SDRAM CAS\ Latency Cycles */
#define SH7750_WCR2_SDRAM_CAS_LAT1  1	/* 1 cycle */
#define SH7750_WCR2_SDRAM_CAS_LAT2  2	/* 2 cycles */
#define SH7750_WCR2_SDRAM_CAS_LAT3  3	/* 3 cycles */
#define SH7750_WCR2_SDRAM_CAS_LAT4  4	/* 4 cycles */
#define SH7750_WCR2_SDRAM_CAS_LAT5  5	/* 5 cycles */

/* Wait Control Register 3 - WCR3 */
#define SH7750_WCR3_REGOFS    0x800010	/* offset */
#define SH7750_WCR3           SH7750_P4_REG32(SH7750_WCR3_REGOFS)
#define SH7750_WCR3_A7        SH7750_A7_REG32(SH7750_WCR3_REGOFS)

#define SH7750_WCR3_A6S       0x04000000	/* Area 6 Write Strobe Setup time */
#define SH7750_WCR3_A6H       0x03000000	/* Area 6 Data Hold Time */
#define SH7750_WCR3_A6H_S     24
#define SH7750_WCR3_A5S       0x00400000	/* Area 5 Write Strobe Setup time */
#define SH7750_WCR3_A5H       0x00300000	/* Area 5 Data Hold Time */
#define SH7750_WCR3_A5H_S     20
#define SH7750_WCR3_A4S       0x00040000	/* Area 4 Write Strobe Setup time */
#define SH7750_WCR3_A4H       0x00030000	/* Area 4 Data Hold Time */
#define SH7750_WCR3_A4H_S     16
#define SH7750_WCR3_A3S       0x00004000	/* Area 3 Write Strobe Setup time */
#define SH7750_WCR3_A3H       0x00003000	/* Area 3 Data Hold Time */
#define SH7750_WCR3_A3H_S     12
#define SH7750_WCR3_A2S       0x00000400	/* Area 2 Write Strobe Setup time */
#define SH7750_WCR3_A2H       0x00000300	/* Area 2 Data Hold Time */
#define SH7750_WCR3_A2H_S     8
#define SH7750_WCR3_A1S       0x00000040	/* Area 1 Write Strobe Setup time */
#define SH7750_WCR3_A1H       0x00000030	/* Area 1 Data Hold Time */
#define SH7750_WCR3_A1H_S     4
#define SH7750_WCR3_A0S       0x00000004	/* Area 0 Write Strobe Setup time */
#define SH7750_WCR3_A0H       0x00000003	/* Area 0 Data Hold Time */