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<dd><pre class="Code"><b><a name="84599">STATUS intLibInit(<i class="textVariable">nLevels</i>, <i class="textVariable">nVecs</i>, <i class="textVariable">mode</i>)</a></b></pre></dl><dl class="margin"><dd><p class="Body"><a name="84600"> </a>This routine initializes the interrupt architecture library. It is usually called from <b class="routine"><i class="routine">sysHwInit2</i></b><b>( )</b> in the BSP code. The <i class="textVariable">mode</i> argument specifies whether interrupts are handled in preemptive mode (<b class="symbol_UC">INT_PREEMPT_MODEL</b>) or non-preemptive mode (<b class="symbol_UC">INT_NON_PREEMPT_MODEL</b>).</p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84601"><b class="routine"><i class="routine">intEnable</i></b><b>( )</b> and <b class="routine"><i class="routine">intDisable</i></b><b>( )</b> </a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84602"> </a>The <b class="routine"><i class="routine">intEnable</i></b><b>( )</b> and <b class="routine"><i class="routine">intDisable</i></b><b>( )</b> calls affect the masking of interrupts in the BSP interrupt controller and do not affect the CPU interrupt mask.</p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84603"><b class="routine"><i class="routine">intVecSet</i></b><b>( )</b> and <b class="routine"><i class="routine">intVecGet</i></b><b>( )</b> </a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84604"> </a>Not supported, not present.</p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84605"><b class="routine"><i class="routine">intLockLevelSet</i></b><b>( )</b> and <b class="routine"><i class="routine">intLockLevelGet</i></b><b>( )</b> </a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84606"> </a>Not supported. Present, but not functional. </p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84607"><b class="routine"><i class="routine">intVecBaseSet</i></b><b>( )</b> and <b class="routine"><i class="routine">intVecBaseGet</i></b><b>( )</b> </a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84608"> </a>Not supported. Present, but not functional. </p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84609"><b class="routine"><i class="routine">intUninitVecSet</i></b><b>( )</b> </a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84610"> </a>The user can use this function to install a default interrupt handler for all uninitialized interrupt vectors. The routine is called with the vector number as a single argument.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84611"><b class="symbol_lc">mmuALib</b> </a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84612"> </a>The routine <b class="routine"><i class="routine">mmuReadId</i></b><b>( )</b> is provided on processors with MMUs to return the processor ID (the SA-110, the SA-1100, the ARM-710A, and the ARM-810). This routine is not available on the ARM-7TDMI, as it has no MMU to return the processor ID.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84613"><b class="symbol_lc">usrLib</b> </a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84615"> </a>The interrupt stack display produced by <b class="routine"><i class="routine">checkStack</i></b><b>( )</b>in the target shell shows two interrupt stacks. For details, see section <a href="x-arm5.html#84696"><i class="title">Interrupt stacks</i></a>.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84619"><b class="symbol_lc">vmLib</b> </a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84620"> </a>As mentioned above for <b class="library">cacheLib</b>, caching and virtual memory are linked on ARM processors. Use of <b class="library">vmLib</b> requires that <b class="library">cacheLib</b> be included as well and that calls to the two libraries be coordinated. See <a href="x-arm5.html#84744"><i class="title">Memory Management Unit</i></a>.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84624"><b class="symbol_lc">vxALib</b> </a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84625"> </a>The test-and-set primitive <b class="routine"><i class="routine">vxTas</i></b><b>( )</b><b class="routine"><i class="routine"> </i></b>provides a C-callable interface to the ARM SWPB (swap byte) instruction. </p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84626"><b class="symbol_lc">vxLib</b> </a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84627"> </a>The <b class="routine"><i class="routine">vxMemProbe</i></b><b>( )</b> routine, which probes an address for a bus error, is supported by trapping data aborts. If the BSP hardware does not generate data aborts when illegal addresses are accessed, <b class="routine"><i class="routine">vxMemProbe</i></b><b>( )</b> does not return the expected results, The BSP can provide an alternate routine by inserting the address of the alternate routine in the global variable <b class="symbol_lc">_func_vxMemProbeHook</b>.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84628">COFF-Specific Tools For ARM </a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84629"> </a>The following tools are specific to the <b class="symbol_UC">COFF</b> format on ARM processors. For more information, see the reference entries for each tool.</p></dl><dl class="margin"><dd><div class="Item"><a name="84631"> </a><b class="command">coffHexArm </b></div><dl class="margin"><dd><div class="Indent"><a name="84632"> </a>converts an <b class="symbol_UC">COFF</b>-format object file into Motorola hex records. The syntax is:</div><br><dl class="margin"><dd><pre class="Code3"><b><a name="84633">coffHexArm [-a <i class="textVariable">offset</i>] [-l] <i class="textVariable">file</i> </a></b></pre></dl></dl><dd><div class="Item"><a name="84635"> </a><b class="command">coffArmToBin </b></div><dl class="margin"><dd><div class="Indent"><a name="84636"> </a>extracts text and data segments from a <b class="symbol_UC">COFF</b> file and writes it to standard output as a simple binary image. The syntax is:</div><br><dl class="margin"><dd><pre class="Code3"><b><a name="84637">coffArmToBin < <i class="textVariable">infile</i> > <i class="textVariable">outfile</i> </a></b></pre></dl></dl><dd><div class="Item"><a name="84639"> </a><b class="command">xsymcArm </b></div><dl class="margin"><dd><div class="Indent"><a name="84640"> </a>extracts the symbol table from a <b class="symbol_UC">COFF</b> file. The syntax is:</div><br><dl class="margin"><dd><pre class="Code3"><b><a name="84641">xsymcArm < <i class="textVariable">objMod</i> > <i class="textVariable">symTbl</i> </a></b></pre></dl></dl></dl></dl><a name="foot"><hr></a><p class="navbar" align="right"><a href="index.html"><img border="0" alt="[Contents]" src="icons/contents.gif"></a><a href="GuideIX.html"><img border="0" alt="[Index]" src="icons/index.gif"></a><a href="x-arm.html"><img border="0" alt="[Top]" src="icons/top.gif"></a><a href="x-arm3.html"><img border="0" alt="[Prev]" src="icons/prev.gif"></a><a href="x-arm5.html"><img border="0" alt="[Next]" src="icons/next.gif"></a></p></body></html><!---by WRS Documentation (), Wind River Systems, Inc. conversion tool: Quadralay WebWorks Publisher 4.0.11 template: CSS Template, Jan 1998 - Jefro --->⌨️ 快捷键说明
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