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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN"><html><head><link rel="STYLESHEET" type="text/css" href="wrs.css"><title> Intel i960 </title></head><body bgcolor="FFFFFF"><p class="navbar" align="right"><a href="index.html"><img border="0" alt="[Contents]" src="icons/contents.gif"></a><a href="GuideIX.html"><img border="0" alt="[Index]" src="icons/index.gif"></a><a href="x-960.html"><img border="0" alt="[Top]" src="icons/top.gif"></a><a href="x-9603.html"><img border="0" alt="[Prev]" src="icons/prev.gif"></a><a href="x-ix86.html"><img border="0" alt="[Next]" src="icons/next.gif"></a></p><font face="Helvetica, sans-serif" class="sans"><h3 class="H2"><i><a name="84606">C.4 Architecture Considerations</a></i></h3></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84607"> </a>This section describes the following characteristics of the i960 architecture that you should keep in mind as you write a VxWorks application:</p></dl><dl class="margin"><ul class="BulletSingle" type="disc"><li><a name="84608"> </a>Byte order </li></ul><ul class="BulletSingle" type="disc"><li><a name="84609"> </a>Double-word Integers </li></ul><ul class="BulletSingle" type="disc"><li><a name="84610"> </a>VMEbus interrupt handling </li></ul><ul class="BulletSingle" type="disc"><li><a name="84611"> </a>Memory layout </li></ul></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84613">Byte Order</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84614"> </a>The i960 architecture uses little-endian byte order. For information about macros and routines to convert byte order (from big-endian to little-endian and vice versa), see <i class="title">VxWorks Network Programmer's Guide: TCP/IP Under VxWorks</i>.</p><dd><p class="Body"><a name="84615"> </a>The VxWorks loader allows object module headers to be in either big-endian or little-endian byte order. Host utility programs can use the most convenient byte order to process i960 objects. Object file text and data segments must be little endian for i960 processors.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84616">Double-word Integers: <b class="symbol_lc">long long</b> </a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84618"> </a>The double-word integer <b class="symbol_lc">long long</b> is not supported, except as an artifact of your particular architecture and compiler. For more information about handling unsupported features, please see the <i class="title">Customer Support User's Guide</i>.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84620">VMEbus Interrupt Handling</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84621"> </a>The i960 uses 31 interrupt levels instead of the seven used by VMEbus. The mapping of the seven VMEbus interrupts to the 31 i960 levels is board dependent. VMEbus interrupts must be acknowledged with <b class="routine"><i class="routine">sysBusIntAck</i></b><b>( )</b>. VxWorks does not use the vector submitted by the interrupting device. For more information, see the file <i class="textVariable">installDir</i><b class="file">/target/h/arch/i960/ivI960.h</b>.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84623">Memory Layout</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84624"> </a>The figures on the following pages show the layout of a VxWorks system in memory for various target architectures. Areas contain the following labels:<p class="table"><table border="0" cellpadding="0" cellspacing="0"><tr><td colspan="20"><hr class="tablerule"></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84969"> </a>Interrupt Vector Table </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84971"> </a>Table of exception/interrupt vectors.</p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84973"> </a>SM Anchor </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84975"> </a>Anchor for the shared memory network (if there is shared memory on the board).</p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84977"> </a>Boot Line </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84979"> </a>ASCII string of boot parameters.</p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84981"> </a>Exception Message </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84983"> </a>ASCII string of the fatal exception message.</p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84985"> </a>Initial Stack </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84987"> </a>Initial stack for <b class="routine"><i class="routine">usrInit</i></b><b>(</b> <b>)</b>, until <b class="routine"><i class="routine">usrRoot</i></b><b>(</b> <b>)</b> gets allocated stack.</p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84989"> </a>System Image </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84991"> </a>Entry point for VxWorks.</p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84993"> </a>WDB Memory Pool </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84995"> </a>Size depends on the macro <b class="symbol_UC">WDB_POOL_SIZE</b> which defaults to one-sixteenth of the system memory pool. This space is used by the target server to support host-based tools. Modify <b class="symbol_UC">WDB_POOL_SIZE</b> under <b class="symbol_UC">INCLUDE_WDB</b>.</p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84997"> </a>Interrupt Stack </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84999"> </a>Location depends on system image size. Size is defined by <b class="symbol_UC">ISR_STACK_SIZE</b> under <b class="symbol_UC">INCLUDE_KERNEL</b>. </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85001"> </a>System Memory Pool </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85003"> </a>Size depends on size of system image and interrupt stack. The end of the free memory pool for this board is returned by <b class="routine"><i class="routine">sysMemTop</i></b><b>(</b> <b>)</b>.</p></td></tr><tr><td colspan="20"><hr class="tablerule"></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p></p><dd><p class="Body"><a name="84723"> </a><a href="x-9604.html#84651">Figure C-2</a> shows the memory layout for an i960CA target; <div class="frame"><h4 class="EntityTitle"><a name="84651"><font face="Helvetica, sans-serif" size="-1" class="sans">Figure C-2: VxWorks System Memory Layout (i960CA)</font></a></h4><dl class="margin"><div class="Anchor"><a name="84719"> </a><img class="figure" border="0" src="images/x-9600.gif"></div></dl></div><a href="x-9604.html#84728">Figure C-3</a> shows the memory layout for an i960JX target;<div class="frame"><h4 class="EntityTitle"><a name="84728"><font face="Helvetica, sans-serif" size="-1" class="sans">Figure C-3: VxWorks System Memory Layout (i960JX)</font></a></h4><dl class="margin"><div class="Anchor"><a name="84793"> </a><img class="figure" border="0" src="images/x-960a1.gif"></div></dl></div> <a href="x-9604.html#84803">Figure C-4</a> shows the memory layout for an i960KA or i960KB target.<div class="frame"><h4 class="EntityTitle"><a name="84803"><font face="Helvetica, sans-serif" size="-1" class="sans">Figure C-4: VxWorks System Memory Layout (i960KA and i960KB)</font></a></h4><dl class="margin"><div class="Anchor"><a name="84879"> </a><img class="figure" border="0" src="images/x-960a2.gif"></div></dl></div></p><dd><p class="Body"><a name="84880"> </a>All addresses shown in these figures are relative to the start of memory for a particular target board. The start of memory (corresponding to 0x0 in the memory-layout diagram) is defined as <b class="symbol_UC">LOCAL_MEM_LOCAL_ADRS</b> under <b class="symbol_UC">INCLUDE_MEMORY_CONFIG</b> for each target.</p><dd><p class="Body"><a name="79990"> </a></p></dl></dl><a name="foot"><hr></a><p class="navbar" align="right"><a href="index.html"><img border="0" alt="[Contents]" src="icons/contents.gif"></a><a href="GuideIX.html"><img border="0" alt="[Index]" src="icons/index.gif"></a><a href="x-960.html"><img border="0" alt="[Top]" src="icons/top.gif"></a><a href="x-9603.html"><img border="0" alt="[Prev]" src="icons/prev.gif"></a><a href="x-ix86.html"><img border="0" alt="[Next]" src="icons/next.gif"></a></p></body></html><!---by WRS Documentation (), Wind River Systems, Inc. conversion tool: Quadralay WebWorks Publisher 4.0.11 template: CSS Template, Jan 1998 - Jefro --->⌨️ 快捷键说明
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