dds.tan.qmsg

能完全模拟DDS芯片的工作

{ "Info" "ITDB_TH_RESULT" "bell~reg0 key\[0\] clk 6.943 ns register " "Info: th for register \"bell~reg0\" (data pin = \"key\[0\]\", clock pin = \"clk\") is 6.943 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.560 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 13.560 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 12; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns cp_65k 2 REG LC_X2_Y2_N7 25 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y2_N7; Fanout = 25; REG Node = 'cp_65k'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk cp_65k } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.457 ns) + CELL(1.294 ns) 8.475 ns cp_1k 3 REG LC_X2_Y1_N0 19 " "Info: 3: + IC(3.457 ns) + CELL(1.294 ns) = 8.475 ns; Loc. = LC_X2_Y1_N0; Fanout = 19; REG Node = 'cp_1k'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.751 ns" { cp_65k cp_1k } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.167 ns) + CELL(0.918 ns) 13.560 ns bell~reg0 4 REG LC_X3_Y4_N8 2 " "Info: 4: + IC(4.167 ns) + CELL(0.918 ns) = 13.560 ns; Loc. = LC_X3_Y4_N8; Fanout = 2; REG Node = 'bell~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.085 ns" { cp_1k bell~reg0 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 82 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 34.43 % ) " "Info: Total cell delay = 4.669 ns ( 34.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.891 ns ( 65.57 % ) " "Info: Total interconnect delay = 8.891 ns ( 65.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.560 ns" { clk cp_65k cp_1k bell~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.560 ns" { clk clk~combout cp_65k cp_1k bell~reg0 } { 0.000ns 0.000ns 1.267ns 3.457ns 4.167ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 82 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.838 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.838 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns key\[0\] 1 PIN PIN_61 27 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_61; Fanout = 27; PIN Node = 'key\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { key[0] } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.645 ns) + CELL(1.061 ns) 6.838 ns bell~reg0 2 REG LC_X3_Y4_N8 2 " "Info: 2: + IC(4.645 ns) + CELL(1.061 ns) = 6.838 ns; Loc. = LC_X3_Y4_N8; Fanout = 2; REG Node = 'bell~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.706 ns" { key[0] bell~reg0 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 82 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 32.07 % ) " "Info: Total cell delay = 2.193 ns ( 32.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.645 ns ( 67.93 % ) " "Info: Total interconnect delay = 4.645 ns ( 67.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.838 ns" { key[0] bell~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.838 ns" { key[0] key[0]~combout bell~reg0 } { 0.000ns 0.000ns 4.645ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.560 ns" { clk cp_65k cp_1k bell~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.560 ns" { clk clk~combout cp_65k cp_1k bell~reg0 } { 0.000ns 0.000ns 1.267ns 3.457ns 4.167ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.838 ns" { key[0] bell~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.838 ns" { key[0] key[0]~combout bell~reg0 } { 0.000ns 0.000ns 4.645ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "101 " "Info: Allocated 101 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 16 16:36:27 2009 " "Info: Processing ended: Mon Feb 16 16:36:27 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}