📄 dds.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 9 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cp_1k " "Info: Detected ripple clock \"cp_1k\" as buffer" { } { { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 21 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "cp_1k" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cp_65k " "Info: Detected ripple clock \"cp_65k\" as buffer" { } { { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 19 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "cp_65k" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register dds_m\[3\] register dds_add\[12\] 88.9 MHz 11.248 ns Internal " "Info: Clock \"clk\" has Internal fmax of 88.9 MHz between source register \"dds_m\[3\]\" and destination register \"dds_add\[12\]\" (period= 11.248 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.078 ns + Longest register register " "Info: + Longest register to register delay is 5.078 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds_m\[3\] 1 REG LC_X3_Y2_N2 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N2; Fanout = 7; REG Node = 'dds_m\[3\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds_m[3] } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.937 ns) + CELL(0.747 ns) 2.684 ns dds_add\[3\]~183 2 COMB LC_X3_Y3_N5 2 " "Info: 2: + IC(1.937 ns) + CELL(0.747 ns) = 2.684 ns; Loc. = LC_X3_Y3_N5; Fanout = 2; COMB Node = 'dds_add\[3\]~183'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.684 ns" { dds_m[3] dds_add[3]~183 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 69 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.807 ns dds_add\[4\]~182 3 COMB LC_X3_Y3_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.807 ns; Loc. = LC_X3_Y3_N6; Fanout = 2; COMB Node = 'dds_add\[4\]~182'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { dds_add[3]~183 dds_add[4]~182 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 69 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.930 ns dds_add\[5\]~181 4 COMB LC_X3_Y3_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.930 ns; Loc. = LC_X3_Y3_N7; Fanout = 2; COMB Node = 'dds_add\[5\]~181'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { dds_add[4]~182 dds_add[5]~181 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 69 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 3.053 ns dds_add\[6\]~180 5 COMB LC_X3_Y3_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 3.053 ns; Loc. = LC_X3_Y3_N8; Fanout = 2; COMB Node = 'dds_add\[6\]~180'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { dds_add[5]~181 dds_add[6]~180 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 69 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 3.452 ns dds_add\[7\]~179 6 COMB LC_X3_Y3_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 3.452 ns; Loc. = LC_X3_Y3_N9; Fanout = 6; COMB Node = 'dds_add\[7\]~179'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.399 ns" { dds_add[6]~180 dds_add[7]~179 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 69 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.626 ns) 5.078 ns dds_add\[12\] 7 REG LC_X4_Y3_N4 38 " "Info: 7: + IC(0.000 ns) + CELL(1.626 ns) = 5.078 ns; Loc. = LC_X4_Y3_N4; Fanout = 38; REG Node = 'dds_add\[12\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.626 ns" { dds_add[7]~179 dds_add[12] } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 69 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.141 ns ( 61.86 % ) " "Info: Total cell delay = 3.141 ns ( 61.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.937 ns ( 38.14 % ) " "Info: Total interconnect delay = 1.937 ns ( 38.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.078 ns" { dds_m[3] dds_add[3]~183 dds_add[4]~182 dds_add[5]~181 dds_add[6]~180 dds_add[7]~179 dds_add[12] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.078 ns" { dds_m[3] dds_add[3]~183 dds_add[4]~182 dds_add[5]~181 dds_add[6]~180 dds_add[7]~179 dds_add[12] } { 0.000ns 1.937ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.123ns 0.399ns 1.626ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.461 ns - Smallest " "Info: - Smallest clock skew is -5.461 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.099 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 12; CLK Node = 'clk'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns cp_65k 2 REG LC_X2_Y2_N7 25 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y2_N7; Fanout = 25; REG Node = 'cp_65k'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk cp_65k } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.457 ns) + CELL(0.918 ns) 8.099 ns dds_add\[12\] 3 REG LC_X4_Y3_N4 38 " "Info: 3: + IC(3.457 ns) + CELL(0.918 ns) = 8.099 ns; Loc. = LC_X4_Y3_N4; Fanout = 38; REG Node = 'dds_add\[12\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.375 ns" { cp_65k dds_add[12] } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 69 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.67 % ) " "Info: Total cell delay = 3.375 ns ( 41.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.724 ns ( 58.33 % ) " "Info: Total interconnect delay = 4.724 ns ( 58.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.099 ns" { clk cp_65k dds_add[12] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.099 ns" { clk clk~combout cp_65k dds_add[12] } { 0.000ns 0.000ns 1.267ns 3.457ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.560 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 13.560 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 12; CLK Node = 'clk'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns cp_65k 2 REG LC_X2_Y2_N7 25 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y2_N7; Fanout = 25; REG Node = 'cp_65k'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk cp_65k } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.457 ns) + CELL(1.294 ns) 8.475 ns cp_1k 3 REG LC_X2_Y1_N0 19 " "Info: 3: + IC(3.457 ns) + CELL(1.294 ns) = 8.475 ns; Loc. = LC_X2_Y1_N0; Fanout = 19; REG Node = 'cp_1k'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.751 ns" { cp_65k cp_1k } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.167 ns) + CELL(0.918 ns) 13.560 ns dds_m\[3\] 4 REG LC_X3_Y2_N2 7 " "Info: 4: + IC(4.167 ns) + CELL(0.918 ns) = 13.560 ns; Loc. = LC_X3_Y2_N2; Fanout = 7; REG Node = 'dds_m\[3\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.085 ns" { cp_1k dds_m[3] } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 34.43 % ) " "Info: Total cell delay = 4.669 ns ( 34.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.891 ns ( 65.57 % ) " "Info: Total interconnect delay = 8.891 ns ( 65.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.560 ns" { clk cp_65k cp_1k dds_m[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.560 ns" { clk clk~combout cp_65k cp_1k dds_m[3] } { 0.000ns 0.000ns 1.267ns 3.457ns 4.167ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.099 ns" { clk cp_65k dds_add[12] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.099 ns" { clk clk~combout cp_65k dds_add[12] } { 0.000ns 0.000ns 1.267ns 3.457ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.560 ns" { clk cp_65k cp_1k dds_m[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.560 ns" { clk clk~combout cp_65k cp_1k dds_m[3] } { 0.000ns 0.000ns 1.267ns 3.457ns 4.167ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 82 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 69 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.078 ns" { dds_m[3] dds_add[3]~183 dds_add[4]~182 dds_add[5]~181 dds_add[6]~180 dds_add[7]~179 dds_add[12] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.078 ns" { dds_m[3] dds_add[3]~183 dds_add[4]~182 dds_add[5]~181 dds_add[6]~180 dds_add[7]~179 dds_add[12] } { 0.000ns 1.937ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.123ns 0.399ns 1.626ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.099 ns" { clk cp_65k dds_add[12] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.099 ns" { clk clk~combout cp_65k dds_add[12] } { 0.000ns 0.000ns 1.267ns 3.457ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.560 ns" { clk cp_65k cp_1k dds_m[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.560 ns" { clk clk~combout cp_65k cp_1k dds_m[3] } { 0.000ns 0.000ns 1.267ns 3.457ns 4.167ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "dds_m\[7\] key\[0\] clk -2.518 ns register " "Info: tsu for register \"dds_m\[7\]\" (data pin = \"key\[0\]\", clock pin = \"clk\") is -2.518 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.709 ns + Longest pin register " "Info: + Longest pin to register delay is 10.709 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns key\[0\] 1 PIN PIN_61 27 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_61; Fanout = 27; PIN Node = 'key\[0\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { key[0] } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.681 ns) + CELL(0.747 ns) 5.560 ns Add3~669 2 COMB LC_X7_Y2_N1 2 " "Info: 2: + IC(3.681 ns) + CELL(0.747 ns) = 5.560 ns; Loc. = LC_X7_Y2_N1; Fanout = 2; COMB Node = 'Add3~669'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.428 ns" { key[0] Add3~669 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 5.683 ns Add3~666 3 COMB LC_X7_Y2_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 5.683 ns; Loc. = LC_X7_Y2_N2; Fanout = 2; COMB Node = 'Add3~666'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add3~669 Add3~666 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 5.806 ns Add3~660 4 COMB LC_X7_Y2_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 5.806 ns; Loc. = LC_X7_Y2_N3; Fanout = 2; COMB Node = 'Add3~660'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add3~666 Add3~660 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 6.067 ns Add3~663 5 COMB LC_X7_Y2_N4 5 " "Info: 5: + IC(0.000 ns) + CELL(0.261 ns) = 6.067 ns; Loc. = LC_X7_Y2_N4; Fanout = 5; COMB Node = 'Add3~663'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { Add3~660 Add3~663 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 7.042 ns Add3~650 6 COMB LC_X7_Y2_N7 1 " "Info: 6: + IC(0.000 ns) + CELL(0.975 ns) = 7.042 ns; Loc. = LC_X7_Y2_N7; Fanout = 1; COMB Node = 'Add3~650'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.975 ns" { Add3~663 Add3~650 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.076 ns) + CELL(0.591 ns) 10.709 ns dds_m\[7\] 7 REG LC_X2_Y3_N5 6 " "Info: 7: + IC(3.076 ns) + CELL(0.591 ns) = 10.709 ns; Loc. = LC_X2_Y3_N5; Fanout = 6; REG Node = 'dds_m\[7\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.667 ns" { Add3~650 dds_m[7] } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.952 ns ( 36.90 % ) " "Info: Total cell delay = 3.952 ns ( 36.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.757 ns ( 63.10 % ) " "Info: Total interconnect delay = 6.757 ns ( 63.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.709 ns" { key[0] Add3~669 Add3~666 Add3~660 Add3~663 Add3~650 dds_m[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.709 ns" { key[0] key[0]~combout Add3~669 Add3~666 Add3~660 Add3~663 Add3~650 dds_m[7] } { 0.000ns 0.000ns 3.681ns 0.000ns 0.000ns 0.000ns 0.000ns 3.076ns } { 0.000ns 1.132ns 0.747ns 0.123ns 0.123ns 0.261ns 0.975ns 0.591ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 82 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.560 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 13.560 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 12; CLK Node = 'clk'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns cp_65k 2 REG LC_X2_Y2_N7 25 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y2_N7; Fanout = 25; REG Node = 'cp_65k'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk cp_65k } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.457 ns) + CELL(1.294 ns) 8.475 ns cp_1k 3 REG LC_X2_Y1_N0 19 " "Info: 3: + IC(3.457 ns) + CELL(1.294 ns) = 8.475 ns; Loc. = LC_X2_Y1_N0; Fanout = 19; REG Node = 'cp_1k'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.751 ns" { cp_65k cp_1k } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.167 ns) + CELL(0.918 ns) 13.560 ns dds_m\[7\] 4 REG LC_X2_Y3_N5 6 " "Info: 4: + IC(4.167 ns) + CELL(0.918 ns) = 13.560 ns; Loc. = LC_X2_Y3_N5; Fanout = 6; REG Node = 'dds_m\[7\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.085 ns" { cp_1k dds_m[7] } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 34.43 % ) " "Info: Total cell delay = 4.669 ns ( 34.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.891 ns ( 65.57 % ) " "Info: Total interconnect delay = 8.891 ns ( 65.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.560 ns" { clk cp_65k cp_1k dds_m[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.560 ns" { clk clk~combout cp_65k cp_1k dds_m[7] } { 0.000ns 0.000ns 1.267ns 3.457ns 4.167ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.709 ns" { key[0] Add3~669 Add3~666 Add3~660 Add3~663 Add3~650 dds_m[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.709 ns" { key[0] key[0]~combout Add3~669 Add3~666 Add3~660 Add3~663 Add3~650 dds_m[7] } { 0.000ns 0.000ns 3.681ns 0.000ns 0.000ns 0.000ns 0.000ns 3.076ns } { 0.000ns 1.132ns 0.747ns 0.123ns 0.123ns 0.261ns 0.975ns 0.591ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.560 ns" { clk cp_65k cp_1k dds_m[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.560 ns" { clk clk~combout cp_65k cp_1k dds_m[7] } { 0.000ns 0.000ns 1.267ns 3.457ns 4.167ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[5\] dds_add\[14\] 21.472 ns register " "Info: tco from clock \"clk\" to destination pin \"data\[5\]\" through register \"dds_add\[14\]\" is 21.472 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.099 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 12; CLK Node = 'clk'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns cp_65k 2 REG LC_X2_Y2_N7 25 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y2_N7; Fanout = 25; REG Node = 'cp_65k'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk cp_65k } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.457 ns) + CELL(0.918 ns) 8.099 ns dds_add\[14\] 3 REG LC_X4_Y3_N6 41 " "Info: 3: + IC(3.457 ns) + CELL(0.918 ns) = 8.099 ns; Loc. = LC_X4_Y3_N6; Fanout = 41; REG Node = 'dds_add\[14\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.375 ns" { cp_65k dds_add[14] } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 69 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.67 % ) " "Info: Total cell delay = 3.375 ns ( 41.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.724 ns ( 58.33 % ) " "Info: Total interconnect delay = 4.724 ns ( 58.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.099 ns" { clk cp_65k dds_add[14] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.099 ns" { clk clk~combout cp_65k dds_add[14] } { 0.000ns 0.000ns 1.267ns 3.457ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 69 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.997 ns + Longest register pin " "Info: + Longest register to pin delay is 12.997 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds_add\[14\] 1 REG LC_X4_Y3_N6 41 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y3_N6; Fanout = 41; REG Node = 'dds_add\[14\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds_add[14] } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 69 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.949 ns) + CELL(0.914 ns) 1.863 ns data~472 2 COMB LC_X4_Y3_N8 2 " "Info: 2: + IC(0.949 ns) + CELL(0.914 ns) = 1.863 ns; Loc. = LC_X4_Y3_N8; Fanout = 2; COMB Node = 'data~472'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.863 ns" { dds_add[14] data~472 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.563 ns) + CELL(0.511 ns) 4.937 ns data~474 3 COMB LC_X5_Y1_N0 2 " "Info: 3: + IC(2.563 ns) + CELL(0.511 ns) = 4.937 ns; Loc. = LC_X5_Y1_N0; Fanout = 2; COMB Node = 'data~474'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.074 ns" { data~472 data~474 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.798 ns) + CELL(0.511 ns) 6.246 ns data~475 4 COMB LC_X5_Y1_N4 2 " "Info: 4: + IC(0.798 ns) + CELL(0.511 ns) = 6.246 ns; Loc. = LC_X5_Y1_N4; Fanout = 2; COMB Node = 'data~475'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.309 ns" { data~474 data~475 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.780 ns) + CELL(0.511 ns) 7.537 ns data~477 5 COMB LC_X5_Y1_N7 1 " "Info: 5: + IC(0.780 ns) + CELL(0.511 ns) = 7.537 ns; Loc. = LC_X5_Y1_N7; Fanout = 1; COMB Node = 'data~477'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.291 ns" { data~475 data~477 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.511 ns) 8.831 ns data~479 6 COMB LC_X5_Y1_N6 1 " "Info: 6: + IC(0.783 ns) + CELL(0.511 ns) = 8.831 ns; Loc. = LC_X5_Y1_N6; Fanout = 1; COMB Node = 'data~479'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.294 ns" { data~477 data~479 } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.844 ns) + CELL(2.322 ns) 12.997 ns data\[5\] 7 PIN PIN_47 0 " "Info: 7: + IC(1.844 ns) + CELL(2.322 ns) = 12.997 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'data\[5\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.166 ns" { data~479 data[5] } "NODE_NAME" } } { "dds.vhd" "" { Text "E:/CPLD/例程/实际例程/9正弦波发生电路/dds.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.280 ns ( 40.62 % ) " "Info: Total cell delay = 5.280 ns ( 40.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.717 ns ( 59.38 % ) " "Info: Total interconnect delay = 7.717 ns ( 59.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.997 ns" { dds_add[14] data~472 data~474 data~475 data~477 data~479 data[5] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.997 ns" { dds_add[14] data~472 data~474 data~475 data~477 data~479 data[5] } { 0.000ns 0.949ns 2.563ns 0.798ns 0.780ns 0.783ns 1.844ns } { 0.000ns 0.914ns 0.511ns 0.511ns 0.511ns 0.511ns 2.322ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.099 ns" { clk cp_65k dds_add[14] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.099 ns" { clk clk~combout cp_65k dds_add[14] } { 0.000ns 0.000ns 1.267ns 3.457ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.997 ns" { dds_add[14] data~472 data~474 data~475 data~477 data~479 data[5] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.997 ns" { dds_add[14] data~472 data~474 data~475 data~477 data~479 data[5] } { 0.000ns 0.949ns 2.563ns 0.798ns 0.780ns 0.783ns 1.844ns } { 0.000ns 0.914ns 0.511ns 0.511ns 0.511ns 0.511ns 2.322ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
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