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				<p class="header">SD Toolbox Reference</p>
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	<p class="title"><span lang=EN-US style='font-size:24.0pt;color:#990000;
mso-ansi-language:EN-US'>Switch Non-Linearity</span></p>
	<p class="body">Models the non-linear on-resistance of the sampling switch.</p>
	<p class="section">Library</p>
	<p class="body">SD Toolbox.</p>
	<p class="section">Description</p>
	<p class="body">The Switch Non-linearity block models the non-linear on-resistance of the sampling switch assuming a complementary CMOS switch with equally sized N-MOS and P-MOS transistors.</p>
	<p class="figure"><img src="Images/SW.gif" alt="" width="120" border="0"></p>
	<p class="body">The on-conductance of a complementary CMOS switch with equally sized N-MOS and P-MOS transistors, assuming that the input and output voltages are equal is given by</p>
	<p class="equation"><img src="Images/SW_Eq1.gif" alt="" height="43" width="562" border="0"></p>
	<p class="body">where <i>V<sub>in</sub></i> is the input voltage <i>W</i> and <i>L</i> are the width and the length of the transistors, <i>V<sub>thN</sub></i> (positive) and <i>V<sub>thP</sub></i> (negative) are the threshold voltages of the N-MOS and P-MOS transistors, <i>K'<sub>N</sub></i> and <i>K'<sub>P</sub></i> are the gain factors of the N-MOS and P-MOS transistors and <i>V<sub>DD</sub></i> and <i>V<sub>SS</sub></i> are the positive and negative supply voltages used for driving the gates of the N-MOS and P-MOS transistors, respectively.</p>
	<p class="body">This conductance, which depends on the input signal, together with the sampling capacitance <i>C<sub>s</sub></i>, produces a settling transient which leads at the end of the clock cycle (typically after <i>T<sub>s</sub></i>/2) to an output value given by</p>
	<p class="equation"><img src="Images/SW_Eq2.gif" alt="" height="45" width="186" border="0"></p>
	<p class="body">which is in error with respect to the ideal value. This error depends on the input signal and hence gives rise to non-linearity.</p>
	<p class="body">To reduce the non-linearity introduced by the switch the bootstrapping technique is often used. In this case a dedicated circuit drives the gates of the MOS transistors with a voltage dependent on the input signal (e.g. <i>V<sub>DD</sub></i> + <i>V<sub>in</sub></i> in the ideal case) in order to maintain the <i>V<sub>GS</sub></i> constant. Actually the gate voltage cannot be exactly <i>V<sub>DD</sub></i> + <i>V<sub>in</sub></i>, but is typically <i>V<sub>DD</sub></i> + <i>BSV<sub>in</sub></i>, with <i>BS</i> ranging from 0 (no bootstrapping) to 1 (ideal bootstrapping). In this case, the on-resistance of a complementary CMOS switch becomes</p>
	<p class="equation"><img src="Images/SW_Eq3.gif" alt="" height="46" width="688" border="0"></p>
	<p class="body">which is almost independent of the input signal.</p>
	<p class="section">Parameters</p>
	<ul>
		<li class="body"><span class="parameter">Sample Time</span>: Period of the sampling signal in s (T<sub>s</sub> = 1/f<sub>s</sub>, where f<sub>s</sub> is the sampling frequency)
		<li class="body"><span class="parameter">Sampling Capacitance</span>: Value of the sampling capacitance C<sub>s</sub> in F
		<li class="body"><span class="parameter">Positive Supply Voltage</span>: Value of the positive supply voltage used to drive the gate of the N-MOS transistor of the switch (V<sub>DD</sub>) in V<li class="body"><span class="parameter">Negative Supply Voltage</span>: Value of the negative supply voltage used to drive the gate of the P-MOS transistor of the switch (V<sub>SS</sub>) in V<li class="body"><span class="parameter">Transistor Size</span>: Value of the aspect ratio (W/L) of both the N-MOS and P-MOS transistors of the switch<li class="body"><span class="parameter">N-MOS Gain Factor</span>: Value of the gain factor (K'<sub>N</sub> =
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