📄 flash.asm
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call read_pci_byte
and al,NOT 22h
or al,088h
jmp short e_f_common
;-----------------------------------------------------------------------;
; F000_READ_ROM_WRITE_X ;
;-----------------------------------------------------------------------;
; this routine is used to enable F000 ROM. ;
; input : ;
; stack available ;
; register usage : DO NOT destroy any register ;
; NOTE: 1. program chipset registers to enable F000 rom so that any read;
; F000 segment comes from F000 ROM. ;
; 2. in this routine, CS should NOT be assumed as F000. ;
;-----------------------------------------------------------------------;
public f000_read_rom_write_x
f000_read_rom_write_x:
pushf
push ax
cli
mov ah,76h ; read disable
call read_pci_byte
and al,not 80h
jmp short e_f_common
;-----------------------------------------------------------------------;
; F000_READ_X_WRITE_RAM ;
;-----------------------------------------------------------------------;
; this routine is used to make F000 RAM Write enabled. ;
; input : ;
; stack available ;
; register usage : DO NOT destroy any register ;
; NOTE: 1. program chipset registers to make F000 shadow write enabled ;
; so that write goes to F000 shadow RAM. ;
; 2. if read ram and write ram is possible, then make read ram ;
; and write ram. ELSE make write ram, don't care about read. ;
;-----------------------------------------------------------------------;
public f000_read_x_write_ram
f000_read_x_write_ram: ; F000 shadow ram write enabled
pushf
push ax
cli
mov ah,76h ; write enable
call read_pci_byte
or al,0a0h
jmp short e_f_common
;-----------------------------------------------------------------------;
; F000_READ_RAM_WRITE_ROM ;
;-----------------------------------------------------------------------;
; this routine is used to make F000 shadow RAM Read enabled and write ;
; protected. ;
; input : ;
; stack available ;
; register usage : DO NOT destroy any register ;
; NOTE: 1. program chipset registers to make F000 shadow read enabled ;
; and write protected so that read comes from F000 shadow RAM and ;
; write goes to F000 ROM. ;
; 2. this routine code is NOT executed from F000 segment. ;
;-----------------------------------------------------------------------;
public f000_read_ram_write_rom
f000_read_ram_write_rom: ; F000 shadow ram read only
pushf
push ax
cli
mov ah,76h ; read enable/write disable
call read_pci_byte
or al,80h
and al,not 20h
e_f_common:
call write_pci_byte
pop ax
popf
ret
;-----------------------------------------------------------------------;
; MAKE_VPP_HIGH ; Moved to OEMFLASH.ASM
;-----------------------------------------------------------------------;
; MAKE_VPP_LOW ; Moved to OEMFLASH.ASM
;-----------------------------------------------------------------------;
; FLASH_WRITE_ENABLE ;
;-----------------------------------------------------------------------;
; this routine enables write to Flash EPROM in E000,64K and F000,64K ;
; region. ;
; input : ;
; CLI ;
; stack available ;
; output: ;
; none ;
; register usage : DO NOT destroy any register ;
; NOTE: ;
; 1. if KBC pin is used to enable flash write, call "PGM_KBC" ;
; routine, specification of which is as follows: ;
; input : AL command to be output to KBC ;
; output: none ;
; register destroyed : AX ;
; 2. for 50ms delay, call "DELAY_50MS" routine specification of ;
; which is as follows: ;
; input : none ;
; output: none ;
; register destroyed..none ;
; 3. CS should not be assumed to be F000. ;
;-----------------------------------------------------------------------;
extrn oem_flash_write_enable:near
public flash_write_enable
flash_write_enable proc near
; write code here for chipset register programming which controls the
; flash write signal
pushf
push ax
mov ah,045h
call read_sio_byte
and al,11011011b ;BIT5-->0
or al,00000100b ;BIT2-->1 EPROM can be flashed
call write_sio_byte
; call any oem specific stuff
call oem_flash_write_enable ; in OEMFLASH.ASM
pop ax
popf
ret
flash_write_enable endp
;-----------------------------------------------------------------------;
; FLASH_WRITE_DISABLE ;
;-----------------------------------------------------------------------;
; this routine disables write to Flash EPROM in E000,64K and F000,64K ;
; region. ;
; input : ;
; CLI ;
; stack available ;
; output: ;
; none ;
; register usage : DO NOT destroy any register ;
; NOTE: ;
; 1. if KBC pin is used to disable flash write, call "PGM_KBC" ;
; routine, specification of which is as follows: ;
; input : AL command to be output to KBC ;
; output: none ;
; register destroyed : AX ;
; 2. for 50ms delay, call "DELAY_50MS" routine specification of ;
; which is as follows: ;
; input : none ;
; output: none ;
; register destroyed..none ;
; 3. CS should not be assumed to be F000. ;
;-----------------------------------------------------------------------;
extrn oem_flash_write_disable:near
public flash_write_disable
flash_write_disable proc near
; write code here for chipset register programming which controls the
; flash write signal
pushf
push ax
mov ah,045h
call read_sio_byte
and al, 11011011b ;BIT2-->0 EPROM CAN'T BE FLASHED AGAIN
or al, 00100000b ;BIT5-->1
call write_sio_byte
; call any oem specific stuff
call oem_flash_write_disable ; in OEMFLASH.ASM
pop ax
popf
ret
flash_write_disable endp
;-----------------------------------------------------------------------;
; GET_CHIPSET_VALUES ;
;-----------------------------------------------------------------------;
; this routine returns the chipset values. Please read the sample code ;
; below for PCI and ISA chipset for better understanding. ;
; THIS ROUTINE WILL BE CALLED ONLY IN NORMAL BIOS POST/RUNTIME WHILE ;
; UPDATING PnP NVRAM. THIS ROUTINE IS NOT NEEDED IN BOOT BLOCK CODE. ;
; input : ;
; none ;
; output: ;
; NC successful ;
; BX index port where register index should be written ;
; DX data port where data should be written ;
; CL chipset register# ;
; AL current content of chipset register corresponding ;
; to F000 segment. this value will be used to restore ;
; F000 segment status. ;
; AH data to be written to chipset register to disable ;
; F000 shadow (to disable read from F000 shadow and ;
; make F000 shadow write protected.) ;
; CY error ;
; register usage : DO NOT destroy any register except AX, BX, CL, DX ;
;=======================================================================;
if NOT MKF_FLASH_4GB ; if flash access at 4GB selected
; this routine is not needed.
public get_chipset_values
get_chipset_values proc near
pushf
push bx
push eax
mov dx,0cf8h
mov eax,80000074h ; output reg index 74h (DWORD boundary)
out dx,eax ; note that register index is selected
; here and remain selected so that only
; data needs to be read/written to/from
; data port
io_delay
mov dl,0feh ; DX = 0CFEh, data port to access Reg 76h
in al,dx ; AL = current value of SiS 530 reg 76h
; (current status of F000 segment)
mov bl,al
pop eax
mov al,bl ; AL = current value of SiS 530 reg 76h
; (current status of F000 segment)
mov ah,al
and ah,01011111b ; AH = value to be written to Reg 76h
; to disable read from F000 shadow RAM
; and make F000 shadow write protected
pop bx
;; AL = curr value of SiS 530 reg 76h
;; AH = value for SiS 530 reg 76h to disable read from F000 shadow and make F000
;; shadow write protected
;; DX = data port for accessing SiS 530 Reg 76h
popf
clc ;Success
ret
get_chipset_values endp
;---------------------------------------;
endif
;-----------------------------------------------------------------------;
rwbs =1
rwws =1
rwdws =0
rwbns =1
rwwns =0
rwdwns =0
srwbs =0
srwws =0
srwdws =0
excmos =1
apcmos =1
include chpregrw.inc
;*****************************************************************;
;*****************************************************************;
;** **;
;** (C)Copyright 1985-1996, American Megatrends Inc. **;
;** **;
;** All Rights Reserved. **;
;** **;
;** 6145-F, Northbelt Parkway, Norcross, **;
;** **;
;** Georgia - 30071, USA. Phone-(770)-246-8600. **;
;** **;
;*****************************************************************;
;*****************************************************************;
;-----------------------------------------------------------------------;
_text ends
end
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