📄 post.asm
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or al,0eh
call write_pci_byte
;; check if system memory > cacheable size (cache size * 2^7), then disable reg.81 bit 6
call get_total_memory_size
shr eax,10 ; KB base
mov ebx,eax ; save total memory size in ebx
mov ah,51h
call read_pci_byte
test al,80h
jz disable_read_cycle
and al,30h ; keep cache size bits
shr al,4
mov cl,al
mov eax,100h
shl eax,cl
shl eax,7 ; cache size * 2^7
cmp ebx,eax
ja disable_read_cycle
mov ah,81h ; A2's setting
call read_pci_byte
or al,40h
call write_pci_byte
disable_read_cycle:
;----------------------------------------------------------------------------;
;=======================================
; Reg56 modified by SETUP
;=======================================
; mov al, Q_MDLE_DELAY
; call get_cmos_item
; shl al, 04h ; shift to upper 4 bits
; mov bl, al ; get CMOS value save to BL
; mov ah, 056h
; call read_pci_byte
; and al, 00001111b ; Keep other 4 bits!
; or al, bl ; Mask CMOS value with BL
; call write_pci_byte
;=======================================
; Reg80(bit7~bit5) for Mainmum burstable address
;=======================================
mov al,Q_MAX_BURSTABLE
call get_cmos_item
mov bl, al
shl bl, 5 ; get CMOS value save to BL
mov ah, 080h
call read_pci_byte
and al, 00011111b ; Keep other 5 bits!
or al, bl ; Mask CMOS value with BL
call write_pci_byte
mov ax, 08460h
call write_pci_byte
; mov al,Q_PCI_GRANT_TIMER1
; call get_cmos_item
mov ax, 08500h
call write_pci_byte
;=======================================
; Reg86 for CPU Idle Timer for PCI
;=======================================
; mov al,Q_IDLE_TIMER_PCI
; call get_cmos_item
mov ax, 08603h
call write_pci_byte
;; for VGA report memory in AEh, AFh
call get_total_memory_size
shr eax,20
mov bx,ax
mov ah,0aeh
call write_pci_byte
mov ah,0afh
mov al,bh
call write_pci_byte
; Do OEM specific stuff if any
call oem_program_ws
pwsc_skip_setup_prog:
ret
;-----------------------------------------------------------------------;
; SPECIAL_CONFIG_DISPLAY ;
;-----------------------------------------------------------------------;
; check point : AA ;
; this routine is called from system_configuration_display to display ;
; any special configuration. ;
; input : ;
; ds 0040h ;
; es 0000h ;
; stack available ;
; register usage : can destroy any register except EBP,DS,ES,FS,GS ;
;-----------------------------------------------------------------------;
extrn oem_special_config_display:near
extrn ecc_disabled_msg:abs
extrn wait_input_char:near
extrn display_message_set:near
public special_config_display
special_config_display:
; Do chipset specific generic stuff
; Do OEM specific stuff if any
call oem_special_config_display
ret
;-----------------------------------------------------------------------;
; GET_MEM_INFO ;
;-----------------------------------------------------------------------;
; check point : 8C ;
; this routine is called while generating table for INT-15 E820 func. ;
; input : ;
; SS 0030H ;
; DS 0040H ;
; ES 0000H ;
; stack available ;
; output: ;
; cy routine not implemented ;
; nc routine implemented ;
; ESI total memory size in bytes ;
; (example, for 8MB total memory, ESI = 8192*1024bytes) ;
; ECX,EDX memory region1 32-bit start address, size in bytes ;
; EAX,EBX memory region2 32-bit start address, size in bytes ;
; EDI bit-0 = Memory region1 information ;
; 0..memory region1 is a HOLE region ;
; 1..memory region1 is a non-cacheable region ;
; bit-1 = Memory region2 information ;
; 0..memory region2 is a HOLE region ;
; 1..memory region2 is a non-cacheable region ;
; bit-31..2 = Reserved ;
; register usage : can destroy any register except EBP,DS,ES,FS,GS ;
; NOTE: 1. Set both start address and size to 0000 for a region which ;
; does not exist. ;
; 2. This routine should read the chipset registers to return the ;
; parameters (this parameters MUST NOT BE READ FROM CMOS). ;
;-----------------------------------------------------------------------;
public get_mem_info
get_mem_info:
call get_total_memory_size
mov esi,eax
xor eax,eax
xor ebx,ebx
xor ecx,ecx
xor edx,edx
xor edi,edi
ret
;;============================================
;;Input:none
;;outut:eax = physical address
;;============================================
extrn get_bank_size:near
public get_total_memory_size
get_total_memory_size:
xor ebx,ebx
mov cl,0
;;===get the total system memmory
get_mem_loop:
xor eax,eax
mov al,cl
call get_bank_size
add ebx,eax
inc cl
cmp cl,2
jbe short get_mem_loop
;;================================
;; for share memory
;; report memory = total- share
mov ah,63h
call read_pci_byte
test al,40h
jz short share_mem_disable
and ax,00110000b
shr al,04h
mov cl,al
mov al,01h
shl ax,cl
sub bx,ax
share_mem_disable:
;; for share memory
mov eax,ebx
shl eax,20
ret
;-----------------------------------------------------------------------;
; GET_L2_CACHE_INFO ;
;-----------------------------------------------------------------------;
; this routine is called from DMI POST INIT and system configuration ;
; display. ;
; input : ;
; none ;
; stack available ;
; output: ;
; CY routine not implemented ;
; NC routine implemented ;
; AX installed cache size (KB), 40h = 64KB, 200h = 512KB ;
; CX current cache information ;
; bit-15..10 = reserved (must be 0) ;
; bit-9..8 = cache mode ;
; 00 -> write-through, 01 -> write-back ;
; 10 -> reserved, 11 -> unknown ;
; bit-7 = current status ;
; 0 -> disabled, 1 -> enabled ;
; bit-6..5 = physical position relative to CPU ;
; 00 -> inside CPU, 01 -> outside CPU ;
; 10 -> reserved, 11 -> unknown ;
; example: for (al)=2 in P54C, return bit-6..5=01 ;
; for (al)=2 in P6, return bit-6..5=00 ;
; bit-4 = reserved (must be 0) ;
; bit-3 = socket information ;
; 0 = not socketed, 1 = socketed ;
; bit-2..0 = cache level (1 to 8), 1 = L1, 2 = L2 ;
; DX current cache type (bit mapped) ;
; bit-15..7 = reserved (must be 0) ;
; bit-6 = 1 -> asynchronous ;
; bit-5 = 1 -> synchronous ;
; bit-4 = 1 -> pipeline burst ;
; bit-3 = 1 -> burst ;
; bit-2 = 1 -> non-burst ;
; bit-1 = 1 -> unknown ;
; bit-0 = 1 -> reserved (must be 0) ;
; BH cache speed in nanosecs ;
; BL error correction type(See SMBIOS Specification) ;
; DI bit-15..8 = System Cache Type(See SMBIOS Specification)
; bit-7..0 = Associativity (See SMBIOS Specification) ;
; register usage : do not destroy any register except AX, BX, CX, DX, DI
; note: Do not get value from CMOS setup question, read chipset register;
; to get current cache information. ;
;-----------------------------------------------------------------------;
public get_l2_cache_info
public get_external_cache_info
get_external_cache_info:
get_l2_cache_info:
mov ah,51h
call read_pci_byte
;; cx== outside CPU, not socketed, L2
mov cx,0022h
test al,80h ;; test enable
jz L2_not_enable
or cx,0080h
L2_not_enable:
test al,08h ;; test WB
jz L2_not_WB
or cx,0100h
L2_not_WB:
and al,00110000b ;; get cache size
shr al,4h
push cx
mov cl,al
mov bx,0100h ; 100h = 256k
shl bx,cl
mov ax,bx
pop cx
mov dx,0010h
mov bx,0503h
mov di,0103h
clc
ret
;-----------------------------------------------------------------------;
; DMI_MEM_MODULE_INFO ;
;-----------------------------------------------------------------------;
; this routine is called from DMI POST INIT code to return information ;
; about the concerned MEMORY MODULE. ;
; input : ;
; AL memory module# (1 based) ;
; stack available ;
; output: ;
; CY routine not implemented ;
; NC routine implemented ;
; AL memory bank connection ;
; bit-7..4 = lower RAS line ;
; bit-3..0 = upper RAS line ;
; example: if bank connected to RAS 2&3, return (al)=23h;
; AH memory module current speed in ns ;
; example: for 60ns memory return (ah)=3ch (60 decimal);
; CX current memory type (bit mapped) ;
; bit-15..9 = reserved (must be 0) ;
; bit-8 = 1 -> DIMM ;
; bit-7 = 1 -> SIMM ;
; bit-6 = 1 -> ECC ;
; bit-5 = 1 -> Parity ;
; bit-4 = 1 -> EDO ;
; bit-3 = 1 -> fast page mode ;
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