📄 post.asm
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page ,132
title POST HOOKS
;---------------------------------------------------------------;
; NOTE: Do not destroy EBP,FS,GS,SS,DS,ES unless otherwise specified.
;---------------------------------------------------------------;
;*****************************************************************;
;*****************************************************************;
;** **;
;** (C)Copyright 1985-1996, American Megatrends Inc. **;
;** **;
;** All Rights Reserved. **;
;** **;
;** 6145-F, Northbelt Parkway, Norcross, **;
;** **;
;** Georgia - 30071, USA. Phone-(770)-246-8600. **;
;** **;
;*****************************************************************;
;*****************************************************************;
;*****************************************************************;
;---------------------------------------;
include mbiosmac.mac
include mbiosequ.equ
include cf.equ
include setupequ.ext
include makeflag.equ
include devnode.equ
include rt.equ
;---------------------------------------;
extrn PCI_init_begin:byte
extrn PCI_init_end:byte
extrn PISAC_init_begin:byte
extrn PISAC_init_end:byte
extrn PMU_init_begin:byte
extrn PMU_init_end:byte
extrn write_chip_byte_x:near
extrn read_chip_byte_x:near
extrn write_pci_byte:near
extrn read_pci_byte:near
extrn write_sio_byte:near
extrn read_sio_byte:near
extrn write_usb_byte:near
extrn write_pmu_byte:near
extrn check_100mhz_cpu_bus:near
extrn ReadCCR:near
extrn WriteCCR:near
extrn disable_l2_cache:near
;---------------------------------------;
extrn update_stnd_cmos_checksum:near
extrn update_extd_cmos_checksum:near
extrn cmos_data_in:near
extrn cmos_data_in_x:near
extrn cmos_data_out:near
extrn cmos_data_out_x:near
extrn check_cmos_data:near
extrn get_cmos_item:near
extrn check_cmos_8e:near
;---------------------------------------;
cgroup group _text
_text segment word public 'CODE'
assume cs:cgroup
.486p
;---------------------------------------;
public _POST_STARTS
_POST_STARTS label byte ; marks start of module
;-----------------------------------------------------------------------;
; THE HOOKS ARE IN ORDER OF EXECUTION ;
;-----------------------------------------------------------------------;
; GET_SMI_SEG_SIZE ;
;-----------------------------------------------------------------------;
; check point : 07 ;
; this routine is called from RM.ASM while filling CPU related info. ;
; this routine returns SMI code segment value and SMI code segment size;
; for all CPUs supported by the motherboard. ;
; input : ;
; al cpu vendor# for which SMI information is to be returned ;
; ah = 00 for bootstarp CPU ;
; <>00 for application CPU ;
; cl CPU number ;
; edx CPU power-on reset id ;
; ebx bit 15-0 = CPU function field ;
; bit 31-16 = CPU extended function field ;
; stack available ;
; output: ;
; ax SMI code segment size ;
; ebx SMI code segment ;
; register usage..can destroy any register except EBP,DS,ES,FS,GS ;
; ;
; NOTE: ;
; 1. CPU Vendor number is as follows: ;
; 00 = Intel ;
; 01 = Cyrix ;
; 02 = AMD ;
; 03 = IBM ;
; 04 = TI ;
; 05 = UMC ;
; 06-FF..RESERVED for future use ;
; 2. SMI code segment is defined as follows: ;
; 3000h means SMI code is at 3000:0 ;
; A000h means SMI code is at A000:0 ;
; 3800h means SMI code is at 3800:0 ;
; 10000h means SMI code is at 10000:0 i.e. 1M:0 ;
; 3. SMI code segment size is defined as follows: ;
; = 00 SMI Not supported ;
; <>00 SMI code segment size ;
; bit3-0 0000..disabled (SMI not supported) ;
; 0001..4KBytes ;
; 0010..8KBytes ;
; 0011..16KBytes ;
; 0100..32KBytes ;
; 0101..64KBytes ;
; 0110..128KBytes ;
; 0111..256Kbytes ;
; 1000..512KBytes ;
; 1001..1MBytes ;
; 1010..2MBytes ;
; 1011..4MBytes ;
; 1100..8MBytes ;
; 1101..16MBytes ;
; 1110..32MBytes ;
; 1111..4Gbytes ;
; bit15-4 not used (should be returned as 0000) ;
; ;
; 4. this routine is invoked by CALL instruction. ;
; 5. the routine may have to read from CMOS registers to get SMI ;
; code segment and size in case these parameters are setup ;
; configurable. ;
; 6. the CS can not be assumed as F000. ;
;-----------------------------------------------------------------------;
public get_smi_seg_size
get_smi_seg_size proc near
mov al, 05h ;64KB SMI Seg.
mov ebx, 0000A000h ;SMI Seg. @ A000:0
ret
get_smi_seg_size endp
;-----------------------------------------------------------------------;
; CP_INIT ;
;-----------------------------------------------------------------------;
; check_point : 13 ;
; This routine is used to do chipset register initialisation, cache ;
; sizing and testing. ;
; input : ;
; DS 0000H ;
; ES 0000H ;
; stack available ;
; output: ;
; BL bit-0 = 0 cache is bad ;
; 1 cache is good ;
; bit7-1= MUST BE returned as 0 ;
; register usage -- can destroy any register except EBP,DS,ES,FS,GS ;
; Note: 1. this routine MUST NOT DO the memory sizing because memory ;
; sizing is done in init code. ;
; 2. this routine should do cache sizing and testing. Use the ;
; routines GO_TO_FLAT_MODE_STACK and COMEBACK_FROM_FLAT_MODE_STACK;
; for going to and coming back from flat mode. ;
; the L2 cache sizing/testing result can be overridden in ;
; OEM_L2_DETECT_CACHE routine in OEMPOST.ASM file. ;
; Another way is not to do the L2 cache sizing and testing here. ;
; Do the L2 cache sizing/testing OEM_L2_DETECT_CACHE routine in ;
; OEMPOST.ASM file according to the requirement. In that case, the;
; deafult code in OEM_L2_DETECT_CACHE routine must do the L2 cache;
; sizing and testing. And then the deafult code can be modified ;
; according to OEM requirement. ;
; 3. this routine can be used to re-initisalise chipset parameters;
; (which does not affect dram configuration) e.g. dram ws, cache ;
; ws, etc. ;
; 4. this routine MUST NOT TOUCH chipset registers which affects ;
; the dram configuration e.g. page mode, remapping, etc. these ;
; variables must be programmed in the init code and if setup ;
; changes any of this parameters, setup MUST reboot. ;
; 5. This routine can be used to program the chipset register for ;
; base memory size. Base memory size can be controlled by chipset ;
; register bit or by setting non-cacheable region to ATBUS. ;
;-----------------------------------------------------------------------;
extrn oem_detect_l2_cache:near
extrn open_apc_cmos:near
extrn close_apc_cmos:near
public cp_init
cp_init:
; (CORE0210+)>
ifdef MKF_CNVRAM
if MKF_CNVRAM
%out === CNVRAM activated ===
extrn check_cmos_8e:near
call check_cmos_8e ; cmos good ?
jz cmos_is_good ; yes..
call cnvram_to_cmos ; copy cnvram to cmos if cnvram is good
cmos_is_good:
endif; if MKF_CNVRAM
endif; ifdef MKF_CNVRAM
; <(CORE0210+)
;; disable PME0# and PME1#
mov ah,04h
call read_apc_cmos
and al, not 18h ; output mode for GPIO#5, GPIO#10
or al,22h ; set GPIO#5 and GPIO#10
call write_apc_cmos
mov ah,03h
call read_apc_cmos
and al, not 08h ; GPIO#5
call write_apc_cmos
mov ah,07h
call read_apc_cmos
and al, not 80h ; GPIO#10
call write_apc_cmos
mov al,Q_CACHE_TAG
call cmos_data_in
shl al,7
mov bl,al
mov ah,51h
call read_pci_byte
and al,not 80h
or al,bl
call write_pci_byte
;; single read disable for Cyrix CPU
mov ah,52h
call read_pci_byte
push ax
call get_processor_info
pop ax
and al,not 40h
cmp bl,1 ; Cyrix CPU?
jz cyrix_cpu
or al,40h
cyrix_cpu:
call write_pci_byte
call check_cmos_8e ;CMOS checksum good ?
jnz ci_exit ;No, do not program SETUP
test bp, ins_key_err_bit ;<INS> key pressed ?
jnz ci_exit ;Yes, do not program SETUP
cli
cld ;; Clear direction flag
mov bx,offset cgroup:PCI_init_begin
mov cx,offset cgroup:PCI_init_end
sub cx,bx
shr cx,1
cp_init_PCI:
mov ah,byte ptr cs:[bx] ;; Get register index
mov al,byte ptr cs:[bx+1] ;; Get register data
call write_pci_byte
add bx,02h ;; Point to next table entry
loop cp_init_PCI
mov bx,offset cgroup:PISAC_init_begin
mov cx,offset cgroup:PISAC_init_end
sub cx,bx
shr cx,1
cp_init_PIC:
mov ah,byte ptr cs:[bx] ;; Get register index
mov al,byte ptr cs:[bx+1] ;; Get register data
call write_sio_byte
add bx,02h ;; Point to next table entry
loop cp_init_PIC
mov eax,80000964h ;; clear REQUEST before clear ENABLE
mov dx,0cf8h
out dx,eax
jmp short $+2
mov dl,0fch
in eax,dx
jmp short $+2
jmp short $+2
out dx,eax
mov bx,offset cgroup:PMU_init_begin
mov cx,offset cgroup:PMU_init_end
sub cx,bx
shr cx,1
cp_init_PMU:
mov ah,byte ptr cs:[bx] ;; Get register index
mov al,byte ptr cs:[bx+1] ;; Get register data
call write_pmu_byte
add bx,02h ;; Point to next table entry
loop cp_init_PMU
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