📄 runtime.asm
字号:
page ,132
title RUNTIME HOOKS
;---------------------------------------------------------------;
; NOTE: Do not destroy EBP,FS,GS,SS,DS,ES unless otherwise specified.
;---------------------------------------------------------------;
;*****************************************************************;
;*****************************************************************;
;** **;
;** (C)Copyright 1985-1996, American Megatrends Inc. **;
;** **;
;** All Rights Reserved. **;
;** **;
;** 6145-F, Northbelt Parkway, Norcross, **;
;** **;
;** Georgia - 30071, USA. Phone-(770)-246-8600. **;
;** **;
;*****************************************************************;
;*****************************************************************;
;*****************************************************************;
;---------------------------------------;
include mbiosmac.mac
include mbiosequ.equ
include cf.equ
include rt.equ
include setupequ.ext
include makeflag.equ
;---------------------------------------;
extrn flush_internal_cache:near
extrn enable_internal_cache:near
extrn disable_internal_cache:near
extrn check_cmos_data:near
extrn get_cmos_item:near
extrn cmos_data_in:near
extrn cmos_data_in_x:near
extrn cmos_data_out:near
extrn cmos_data_out_x:near
extrn read_sio_byte:near
extrn write_sio_byte:near
extrn write_pci_byte:near
extrn go_to_flat_mode_stack:near
extrn comeback_from_flat_mode_stack:near
;---------------------------------------;
;---------------------------------------;
cgroup group _text
;_text segment word public 'CODE'
_text segment para public 'CODE'
assume cs:cgroup
.486p
;---------------------------------------;
public _RUNTIME_STARTS
_RUNTIME_STARTS label byte ; marks start of module
;-----------------------------------------------------------------------;
; DISABLE_L1_CACHE ;
;-----------------------------------------------------------------------;
; this routine disables internal cache by cpu routine and chipset ;
; programming. ;
; input : ;
; none ;
; stack available ;
; output: ;
; none ;
; register usage : do not destroy any register ;
;-----------------------------------------------------------------------;
public disable_l1_cache
disable_l1_cache:
call disable_internal_cache ; disable internal cache in CPU
; write the code here to disable internal cache thorugh chipset, if needed.
; if the chipset internal cache needs to be disabled before CPU internal
; cache, then change the order.
ret
;-----------------------------------------------------------------------;
; ENABLE_L1_CACHE_WT ;
;-----------------------------------------------------------------------;
; this routine enables internal cache in write-through mode by cpu ;
; routine and chipset programming. ;
; input : ;
; none ;
; stack available ;
; output: ;
; none ;
; register usage : do not destroy any register ;
; NOTE: If L1 cache is Write-Back Only, then JMP to ENABLE_L1_CACHE_WB ;
;-----------------------------------------------------------------------;
public enable_l1_cache_wt
enable_l1_cache_wt:
call enable_internal_cache ; enable internal cache in CPU
; program chipset register to enable internal cache in write-thorugh mode
; if needed. if the chipset internal cache needs to be enabled before
; CPU internal cache, then change the order.
ret
;-----------------------------------------------------------------------;
; ENABLE_L1_CACHE_WB ;
;-----------------------------------------------------------------------;
; this routine enables internal cache in write-back mode by cpu ;
; routine and chipset programming. ;
; input : ;
; none ;
; stack available ;
; output: ;
; none ;
; register usage : do not destroy any register ;
; NOTE: If L1 cache is Write-Thru Only, then JMP to ENABLE_L1_CACHE_WT ;
;-----------------------------------------------------------------------;
public enable_l1_cache_wb
enable_l1_cache_wb:
call enable_internal_cache ; enable internal cache in CPU
; program chipset register to enable internal cache in write-back mode
; if needed. if the chipset internal cache needs to be enabled before
; CPU internal cache, then change the order.
ret
;-----------------------------------------------------------------------;
; DISABLE_L2_CACHE ;
;-----------------------------------------------------------------------;
; this routine disables external cache using chipset programming with ;
; proper flushing. ;
; input : ;
; none ;
; stack available ;
; output: ;
; CX 0000..cache disabling not done ;
; FFFF..cache disabling done ;
; register usage : do not destroy any register except AX CX DX ;
; remember to save 32-bit registers if used ;
;-----------------------------------------------------------------------;
public disable_l2_cache
disable_l2_cache:
xor cx,cx ; cache disabling not done
mov ah,051h
call read_pci_byte
test al, 80h ; Check if cache is disabled.
jz short disable_already ; Cache already disabled.
pushf
call flush_sis596_L2
mov ah,051h
call read_pci_byte
and al,01110111b ;something strange
call write_pci_byte
popf
mov cx,-1
disable_already:
ret
;-----------------------------------------------------------------------;
; ENABLE_L2_CACHE_WT ;
;-----------------------------------------------------------------------;
; this routine enables external cache in write-through mode using ;
; chipset programming with proper flushing. ;
; input : ;
; none ;
; stack available ;
; output: ;
; CX 0000..cache enabling not done ;
; FFFF..cache enabling done ;
; register usage : do not destroy any register except AX CX DX ;
; remember to save 32-bit registers if used ;
; NOTE: If L2 cache is Write-Back Only, then JMP to ENABLE_L2_CACHE_WB.;
; This routine will be called only if L2 cache is good. ;
;-----------------------------------------------------------------------;
public enable_l2_cache_wt
enable_l2_cache_wt:
xor cx, cx
mov ah, 051h
call read_pci_byte ;Read the register from 530.
test al, 10000000b ; not enabled
jnz short enable_wt
test al, 00001000b
jz wt_already
enable_wt:
or al, 11000000b ;L2 cache enable
call write_pci_byte
call flush_sis596_L2
and al, 10110111b
call write_pci_byte
mov cx, -1
wt_already:
ret
;-----------------------------------------------------------------------;
; ENABLE_L2_CACHE_WB ;
;-----------------------------------------------------------------------;
; this routine enables external cache in write-back mode using ;
; chipset programming with proper flushing. ;
; input : ;
; none ;
; stack available ;
; output: ;
; CX 0000..cache enabling not done ;
; FFFF..cache enabling done ;
; register usage : do not destroy any register except AX CX DX ;
; remember to save 32-bit registers if used ;
; NOTE: If L2 cache is Write-Thru Only, then JMP to ENABLE_L2_CACHE_WT ;
; This routine will be called only if L2 cache is good. ;
;-----------------------------------------------------------------------;
public enable_l2_cache_wb
enable_l2_cache_wb:
; call flush_sis596_L2
xor cx, cx ; not done yet
mov ah, 051h
call read_pci_byte ;Read the register from 5591.
test al, 10000000b ; enable?
jz enable_wb
test al, 00001000b
jnz wb_already
enable_wb:
or al, 11000000b ;L2 cache enable, Write back mode
call write_pci_byte
call flush_sis596_L2
or al, 00001000b
call write_pci_byte
mov cx, -1
wb_already:
ret
;-----------------------------------------------------------------------;
; FLUSH_ALL_CACHE ;
;-----------------------------------------------------------------------;
; this routine flushes all cache (internal and external). this routine ;
; is called whenever something is written in shadow ram from core bios.;
; input : ;
; none ;
; stack available ;
; output: ;
; none ;
; register usage : do not destroy any register ;
; Note: ;
; 1. This routine should flush the external cache and internal cache. ;
; The order of flushing may depend on the chipset. ;
; 2. Call FLUSH_INTERNAL_CACHE to flush internal cache. ;
; 3. If flat mode is needed for external cache flushing, use the routine
; GO_TO_FLAT_MODE_STACK to go to flat mode, flush cache and use the ;
; routine COMEBACK_FROM_FLAT_MODE_STACK for coming back to normal mode.;
; 4. If external cache is disabled at this time, do not flush (it will ;
; take time) externl cache. ;
; 5. Write this routine in two parts for example, ;
; a) for external cache flush, write FLUSH_EXTERNAL_CACHE routine,;
; which can also be used from DISABLE_L2_CACHE which needs to ;
; b) flush external cache before disabling the external cache. ;
; for internal cache flush, use FLUSH_INTERNAL_CACHE routine. ;
;-----------------------------------------------------------------------;
public flush_all_cache
flush_all_cache:
call flush_internal_cache ; Call cpu routine to flush
ret
flush_sis596_L2 proc near
pushf
cli
push ds
push es
pushad
mov al,0b3h
call cmos_data_in
test al,01h
jz flush_external_cache_end
mov ah,051h
call read_pci_byte
push ax
call go_to_flat_mode_stack
pop cx
and cl,00110000b ;; get cache size
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -