cpu.cfg

<BIOS研发技术剖析>书的源代码,包括完整的BIOS汇编语言源程序.

;-----------------------------------------------------------------;

	James		equ	0	; = 0 for generic usage
	CORE_626	equ	0	; 0 = 627

;	SHARED_MEMORY	equ	0	; Call program_cx6x86_regs at ckpt 07h
	SHARED_MEMORY	equ	1	; Call program_cx6x86_regs at ckpt 07h and AAh

     	CPU_386		equ	0
     	CPU_486		equ	0
     	CPU_586		equ	1
     	CPU_686		equ	0

     	CPU_INTEL	equ	1
     	CPU_CYRIX	equ	1
					; (CPU0039+)>
	CYRIX_SADS	equ	0	; 1 = SiS/ALi chipset
					; 0 = disabled CCR2 SADS
					; <(CPU0039+)
     	CPU_AMD		equ	1
     	CPU_IBM		equ	0
     	CPU_TI		equ	0
     	CPU_UMC		equ	0
     	CPU_SGS		equ	0
     	CPU_IDT		equ	1
     	CPU_Rise	equ	1	; $$$CPU0014+

     	FP_PROC		equ	0	; = 1 Floating point processors

;--------------------------------------;
; Intel PentiumPro/Pentium-II VGA USWC ;
;--------------------------------------;--------------------------------------;
;	This is to define VGA USWC memory of PentiumPro/Pentium-II.	      ;
;		A000SEGUSWC	- enable/disable A000 segment USWC	      ;
;		B000SEGUSWC	- enable/disable B000 segment USWC	      ;
;									      ;
;	*Note:	This alone will not enable/disable the USWC cache of the VGA  ;
;		segments. "GET_SHADOW_STATUS" hook has to enable VGA USWC.    ;
;-----------------------------------------------------------------------------;
	A000SEGUSWC		EQU	1	; 0=disable, 1=enable
	B000SEGUSWC		EQU	1	; 0=disable, 1=enable


;--------------------------------------------------------------;
; Intel PentiumPro/Pentium-II base memory non cacheable option ;
;--------------------------------------------------------------;-------------;
;	This defines the base memory non cacheability option.		     ;
;		BASE512KNC	- controls 00000-7FFFF memory range	     ;
;		BASE512TO640KNC	- controls 80000-9FFFF memory range	     ;
;----------------------------------------------------------------------------;
	BASE512KNC		EQU	0	; 0=base 512K cached
						; 1=base 512K non cached
	BASE512TO640KNC		EQU	0	; 0=base 512K-640K cached
						; 1=base 512K-640K non cached

;--------------------------------------------------;
; New INT-15 specification for P6 microcode update ;
;--------------------------------------------------;-------------------------;
;	This defines whether new or old spec. INT-15 module is linked for    ;
;	loading function of the PentiumPro/Pentium-II microcode. The INT-15  ;
;	module code is in BUP6.ASM file.				     ;
;----------------------------------------------------------------------------;
	NEWBUPSPEC		EQU	1	; 0=old spec, 1=new spec


;-------------------------------------;
; Pentium-II force 512MB cacheability ;
;-------------------------------------;---------------------------------------;
;	Pentium-II (Klamath) does not support cacheable region beyond 512MB.  ;
;	This defines whether BIOS will set all memory range above 512MB non   ;
;	cacheable or not.						      ;
;-----------------------------------------------------------------------------;
	KLAMATH512MBFORCE	EQU	1	; 0=all memory  cached
						; 1=above 512MB non cached