pcyrix.inc

<BIOS研发技术剖析>书的源代码,包括完整的BIOS汇编语言源程序.

;-----------------------------------------------------------------------------;
;
; Cyrix POST routines
;
;-----------------------------------------------------------------------------;

;-----------------------------------------------------------------------------;
; Cyrix P-Rating
;-----------------------------------------------------------------------------;
; Input:
;	DX	0
; Output:
;	DL	bit 0 = 1 Clock is PRxxx
;		bit 1 = 1 Append Clock to CPU string
;		bit 2 = 1 Don't display clock at checkpoint AA
;	DS:SI	offset of prating table if DL.3=0
;		bit 3 = 1 Get prating value directly from DS:SI
;	DH	ASCII charactor to be append
;		0 = nothing appended
;	CY	no prating
;-----------------------------------------------------------------------------;
cyrix_prating	proc
if (CPU_586)
	mov	ax,word ptr cpu_resetid
	mov	dl,00000010b		; CPU string with xxx(MHz)
	mov	dh,'+'			; PRxxx+
	mov	si,offset cx_m1_pr_tbl
	cmp	ah,5			; M1 class ?
	jz	put_prating		; yes..

	xor	dh,dh			; no '+'
	mov	dl,00000011b		; CPU/Clock
	cmp	ah,6			; M2 class ?
	stc
	jnz	cp_exit			; no.. no prating
					; (CPU0018)>
	call	ReadDIR			; ah = DIR1, al = DIR0
	cmp	ah,MII_DIR1_BASE	; DIR1>=08h (MII) ?
	jb	csmc_not_mii
	mov	dl,00000110b		; bit2=1-no cpu clock, bit1=1-CPU with xxx
csmc_not_mii:
					; (CPU0009)>
;;	mov	bx,cgroup:word ptr cpu_freq
;;	cmp	bx,150			; 150 MHz
;;	je	check_special_m2_clock
;;	cmp	bx,166			; 166 MHz
;;	jne	put_prating
;;
;;check_special_m2_clock:
;;; ah = DIR1, al = DIR0
;;;	call	ReadDIR			; ah = DIR1, al = DIR0
;;	mov	cl,al			; cl = DIR0
;;	and	al,not 08h
;;	cmp	al,51h			; DIR0 = 51h/59h ?
;;	jne	put_prating		; no.. not 2x for 150/166Mhz
;;;	mov	si,offset cx_m2_special_pr_tbl

; Check if M2 special PRating first
	mov	cl,al			; cl = DIR0
	and	cl,00000111b		; keep bit2:0 for clock ratio (1/2/3/4/5 = 2/2.5/3/3.5/4)
	mov	ax,cgroup:word ptr cpu_freq
	; ax = detected clock
	; cl = clock ratio index (1/2/3/4 = 2/2.5/3/3.5)
	mov	si,cgroup:offset m2_special_tbl
next_m2_table:
	cmp	ax,(M2_PR_STRUC ptr cgroup:[si]).clock
	jne	not_match		; clock not in table..
	cmp	cl,(M2_PR_STRUC ptr cgroup:[si]).ratio
	jne	not_match		; ratio not match..
					; (CPU0036)>
;	movzx	ax,(M2_PR_STRUC ptr cgroup:[si]).pr_index
;	mov	ch,sizeof (vPRATINGSTRUC)
;	mul	ch
;	add	ax,offset cgroup:cx_m2_pr_tbl + sizeof (vPRATINGSTRUC).wFreq + 2 ; 2 = number of entries
;	mov	si,ax
	add	si,offset (M2_PR_STRUC).pr_clock
					; <(CPU0036)
	or	dl,08h			; DL.3=1 get prating value from DS:SI
	jmp	short put_prating
not_match:
	add	si,sizeof (M2_PR_STRUC)
	cmp	si,offset cgroup:cx_special_tbl_end
	jb	next_m2_table

; Not special case..
	mov	si,offset cgroup:cx_m2_pr_tbl
					; <(CPU0009)
					; <(CPU0018)
put_prating:

	clc
cp_exit:
endif;	if (CPU_586)
	ret
cyrix_prating	endp


if (CPU_586)
;-----------------------------------------------------------------------------;
cx_m1_pr_tbl:
		dw	6

;		PRATINGSTRUC	{ 80,  '90+ ' }
;		PRATINGSTRUC	{ 100, '120+' }
;		PRATINGSTRUC	{ 110, '133+' }
;		PRATINGSTRUC	{ 120, '150+' }
;		PRATINGSTRUC	{ 133, '166+' }
;		PRATINGSTRUC	{ 200, '200+' } ; 150Mhz, <=200
		vPRATINGSTRUC	{ 80,	90  }
		vPRATINGSTRUC	{ 100,	120 }
		vPRATINGSTRUC	{ 110,	133 }
		vPRATINGSTRUC	{ 120,	150 }
		vPRATINGSTRUC	{ 133,	166 }
		vPRATINGSTRUC	{ 200,	200 } ; 150Mhz, <=200

						; (CPU0018+)>
;-----------------------------------------------;
; 6x86MX PR Rating Table			;
;-----------------------------------------------;
; Cyrix M II-133	 50*2.0=100		;
; Cyrix M II-133	 55*2.0=110		; ^
; Cyrix M II-150	 60*2.0=120		;
; Cyrix M II-150	 50*2.5=125		; ^
; Cyrix M II-166	 66*2.0=133		;
; Cyrix M II-166	 55*2.5=138		;
; Cyrix M II-166	 50*3.0=150		;
; Cyrix M II-166	 60*2.5=150		; ^
; Cyrix M II-200	 75*2.0=150		; (special)
; Cyrix M II-200	 55*3.0=165		;
; Cyrix M II-200	 66*2.5=166		;
; Cyrix M II-233	 83*2.0=166		; (special)
; Cyrix M II-200	 50*3.5=175		;
; Cyrix M II-200	 60*3.0=180		;
; Cyrix M II-233	 75*2.5=188		; (special)
; Cyrix M II-200	 55*3.5=193		; ^
; Cyrix M II-200	 50*4.0=200		; (special)
; Cyrix M II-266	 66*3.0=200		; (special)	; (CPU0038)
; Cyrix M II-233	100*2.0=200		;
; Cyrix M II-266	 83*2.5=208		; (special)
; Cyrix M II-233	 60*3.5=210		;
; Cyrix M II-233	 55*4.0=220		; ^
; Cyrix M II-300	 75*3.0=225		;
; Cyrix M II-300	 90*2.5=225		;		; (CPU0038+)
; Cyrix M II-300	 66*3.5=233		;
; Cyrix M II-300	 95*2.5=237		;		; (CPU0038+)
; Cyrix M II-300	 60*4.0=240		; ^
; Cyrix M II-366	100*2.5=250		; (special)	; (CPU0036)
; Cyrix M II-333	 83*3.0=250		;
; Cyrix M II-333	 75*3.5=263		;
; Cyrix M II-333	 66*4.0=266		; ^
; Cyrix M II-350	 90*3.0=270		; ^      	; (CPU0038+)
; Cyrix M II-400	 95*3.0=285		; 		; (CPU0040)>,(CPU0038+)
; Cyrix M II-400	 83*3.5=292		;		; (CPU0038)
; Cyrix M II-400	 75*4.0=300		; 		; (CPU0038)
; Cyrix M II-433	100*3.0=300		; ^(special)	; (CPU0038), (CPU0036)
; Cyrix M II-433	 90*3.5=315		; ^		; (CPU0038+)
; Cyrix M II-466	 83*4.0=333		;		; (CPU0038+)
; Cyrix M II-466	 95*3.5=333		; ^		; (CPU0038+)
; Cyrix M II-500	100*3.5=350		;		; (CPU0038+)
; Cyrix M II-500	 90*4.0=360		; ^		; (CPU0038+)
; Cyrix M II-533	 95*4.0=380		; ^		; (CPU0038+)
; Cyrix M II-550	100*4.0=400		; ^		; <(CPU0040),(CPU0038+)
;-----------------------------------------------;
clk_20x		equ	01h
clk_25x		equ	02h
clk_30x		equ	03h
clk_35x		equ	04h
clk_40x		equ	05h
;-----------------------------------------------;
M2_PR_STRUC	struc
	clock		dw	?
	ratio		db	?
	pr_clock	dw	?		; (CPU0036)
M2_PR_STRUC	ends
;-----------------------------------------------;
m2_special_tbl	label	byte
	M2_PR_STRUC	{ 150, clk_20x, 200 }
	M2_PR_STRUC	{ 166, clk_20x, 233 }
	M2_PR_STRUC	{ 188, clk_25x, 233 }
	M2_PR_STRUC	{ 200, clk_40x, 200 }
	M2_PR_STRUC	{ 200, clk_30x, 266 }	; (CPU0038+)
	M2_PR_STRUC	{ 208, clk_25x, 266 }
	M2_PR_STRUC	{ 250, clk_25x, 366 }	; (CPU0036+)
	M2_PR_STRUC	{ 300, clk_30x, 433 }	; (CPU0040),(CPU0036+)
cx_special_tbl_end	label	byte

;-----------------------------------------------;
						; <(CPU0018+)

						; (CPU0018)>
cx_m2_pr_tbl	label	byte
		dw	(offset cgroup:cx_m2_pr_tbl_end - offset cgroup:cx_m2_pr_tbl) / sizeof(vPRATINGSTRUC)	; $$$CPU0017
;		        	  MHz   PR
		vPRATINGSTRUC	{ 110,	133 }
		vPRATINGSTRUC	{ 125,	150 }
		vPRATINGSTRUC	{ 150,	166 }
		vPRATINGSTRUC	{ 192,	200 }
		vPRATINGSTRUC	{ 220,	233 }
				      	      	   		; (CPU0017)>
		vPRATINGSTRUC	{ 208,	266 }
		; MII starts
		vPRATINGSTRUC	{ 240,	300 }
		vPRATINGSTRUC	{ 266,	333 }
				      	      	   		; (CPU0038),(CPU0040)>
		vPRATINGSTRUC	{ 270,	350 }
		vPRATINGSTRUC	{ 300,	400 }
		vPRATINGSTRUC	{ 315,	433 }
		vPRATINGSTRUC	{ 333,	466 }
		vPRATINGSTRUC	{ 360,	500 }
		vPRATINGSTRUC	{ 380,	533 }
		vPRATINGSTRUC	{ 400,	550 }
								; <(CPU0038),(CPU0040)
cx_m2_pr_tbl_end	label	byte
								; <(CPU0017)

;;								; (CPU0009)>
;;cx_m2_special_pr_tbl:
;;		dw	2
;;
;;		vPRATINGSTRUC	{ 150,	200 }	; 75*2 = PR200
;;		vPRATINGSTRUC	{ 166,	233 }	; 83*2 = PR233
;;								; <(CPU0009)
						; <(CPU0018)
;-----------------------------------------------------------------------------;
endif;	(CPU_586)




;