📄 44binit.s
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/* *******************************************************
* NAME : 44BINIT.S *
* Version : 10.JAn.2003 *
* Description: *
* C start up codes *
* Configure memory, Initialize ISR ,stacks *
* Initialize C-variables *
* Fill zeros into zero-initialized C-variables *
*******************************************************/
.globl _start.section ".text"
_start: b ResetHandler /*for debug*/
b HandlerUndef /*handlerUndef*/
b HandlerSWI /*SWI interrupt handler*/
b HandlerPabort /*handlerPAbort */
b HandlerDabort /*handlerDAbort */
b . /*handlerReserved */
b IsrIRQ
b HandlerFIQ
ldr pc,=HandlerEINT0 /* mGA H/W interrupt vector table */
ldr pc,=HandlerEINT1
ldr pc,=HandlerEINT2
ldr pc,=HandlerEINT3
ldr pc,=HandlerEINT4567
ldr pc,=HandlerTICK /*mGA*/
b .
b .
ldr pc,=HandlerZDMA0 /*mGB*/
ldr pc,=HandlerZDMA1
ldr pc,=HandlerBDMA0
ldr pc,=HandlerBDMA1
ldr pc,=HandlerWDT
ldr pc,=HandlerUERR01 /*mGB*/
b .
b .
ldr pc,=HandlerTIMER0 /*mGC*/
ldr pc,=HandlerTIMER1
ldr pc,=HandlerTIMER2
ldr pc,=HandlerTIMER3
ldr pc,=HandlerTIMER4
ldr pc,=HandlerTIMER5
b .
b .
ldr pc,=HandlerURXD0
ldr pc,=HandlerURXD1
ldr pc,=HandlerIIC
ldr pc,=HandlerSIO
ldr pc,=HandlerUTXD0
ldr pc,=HandlerUTXD1
b .
b .
ldr pc,=HandlerRTC
b .
b .
b .
b .
b .
b .
b .
ldr pc,=HandlerADC
b .
b .
b .
b .
b .
b .
b .
ldr pc,=EnterPWDN
HandlerFIQ: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleFIQ b Do_Handler
HandlerIRQ: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleIRQ b Do_Handler
HandlerUndef: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleUndef b Do_Handler
HandlerSWI: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleSWI b Do_Handler
HandlerDabort: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleDabort b Do_Handler
HandlerPabort: stmdb r13!,{r0-r8,r12,r14}
ldr r0,=HandlePabort b Do_Handler
HandlerADC: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleADC b Do_Handler
HandlerRTC: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleRTC b Do_Handler
HandlerUTXD1: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleUTXD1 b Do_Handler
HandlerUTXD0: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleUTXD0 b Do_Handler
HandlerSIO: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleSIO b Do_Handler
HandlerIIC: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleIIC b Do_Handler
HandlerURXD1: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleURXD1 b Do_Handler
HandlerURXD0: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleURXD0 b Do_Handler
HandlerTIMER5: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleTIMER5 b Do_Handler
HandlerTIMER4: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleTIMER4 b Do_Handler
HandlerTIMER3: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleTIMER3 b Do_Handler
HandlerTIMER2: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleTIMER2 b Do_Handler
HandlerTIMER1: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleTIMER1 b Do_Handler
HandlerTIMER0: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleTIMER0 b Do_Handler
HandlerUERR01: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleUERR01 b Do_Handler
HandlerWDT: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleWDT b Do_Handler
HandlerBDMA1: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleBDMA1 b Do_Handler
HandlerBDMA0: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleBDMA0 b Do_Handler
HandlerZDMA1: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleZDMA1 b Do_Handler
HandlerZDMA0: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleZDMA0 b Do_Handler
HandlerTICK: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleTICK b Do_Handler
HandlerEINT4567: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleEINT4567 b Do_Handler
HandlerEINT3: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleEINT3 b Do_Handler
HandlerEINT2: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleEINT2 b Do_Handler
HandlerEINT1: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleEINT1 b Do_Handler
HandlerEINT0: stmdb r13!,{r0-r8,r12,r14} ldr r0,=HandleEINT0 b Do_Handler
Do_Handler: ldr r0,[r0] stmfd sp!,{r0}
ldmfd sp!,{pc}
ldmia r13!,{r0-r8,r12,r14} subs pc,r14,#0x4
/*One of the following two routines can be used for non-vectored interrupt.*/
.globl IsrIRQ
IsrIRQ:
stmdb r13!,{r0-r8,r12,r14}
bl IRQ
ldmia r13!,{r0-r8,r12,r14} subs pc,r14,#0x4
IRQ:
sub sp,sp,#4
stmfd sp!,{r8-r9}
ldr r9,I_ISPR ldr r9,[r9]
mov r8,#0x0
F0:
movs r9,r9,lsr #1
bcs F1
add r8,r8,#4
b F0
F1:
ldr r9,HandleADC
add r9,r9,r8
ldr r9,[r9]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
/*****************************************************
* START *
*****************************************************/
ResetHandler:
ldr r0,=WTCON ldr r0,[r0]
ldr r1,=0x0
str r1,[r0]
ldr r0,=INTMSK ldr r0,[r0]
ldr r1,=MASKALL ldr r1,[r1] str r1,[r0]
/* ****************************************************
* Set clock control registers *
*****************************************************/
ldr r0,=LOCKTIME ldr r0,[r0]
ldr r1,=800 /*count = t_lock * Fin (t_lock=200us, Fin=4MHz) = 800*/
str r1,[r0]
ldr r0,=PLLCON ldr r0,[r0] /*temporary setting of PLL*/
ldr r1,=PLLCON_DAT /*Fin=10MHz,Fout=40MHz*/ ldr r1,[r1]
str r1,[r0]
ldr r0,=CLKCON ldr r0,[r0]
ldr r1,=0x7ff8 /*All unit block CLK enable */
str r1,[r0]
/* ****************************************************
* Set memory control registers *
*****************************************************/
adr r0,SMRDATA
ldmia r0,{r1-r13}
ldr r0,=0x01c80000 /*BWSCON Address*/
stmia r0,{r1-r13}
/* ***************************************************
* Initialize stacks *
*****************************************************/ ldr r0,=SVCStack ldr sp, [r0]
bl InitStacks
/* ****************************************************
* Setup IRQ handler *
*****************************************************/
ldr r0,=HandleIRQ /*This routine is needed*/ ldr r0,[r0] ldr r1,=IsrIRQ /*if there isn't 'subs pc,lr,#4' at 0x18, 0x1c*/
str r1,[r0]
BL Main /*Don't use main() because ......*/
B .
/*****************************************************
The function for initializing stack *
/*****************************************************/
InitStacks:
/*Don't use DRAM,such as stmfd,ldmfd......
SVCstack is initialized before
Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1' */
mrs r0,cpsr
bic r0,r0,#0x1F
orr r1,r0,#0xDB /*UNDEFMODE|NOINT*/
msr cpsr,r1 /*UndefMode*/ ldr r2,=UndefStack
ldr sp,[r2]
orr r1,r0,#0xD7 /*ABORTMODE|NOINT*/
msr cpsr,r1 /*AbortMode*/
ldr r2,=AbortStack
ldr sp,[r2]
orr r1,r0,#0xD2 /*IRQMODE|NOINT*/
msr cpsr,r1 /*IRQMode*/
ldr r2,=IRQStack
ldr sp,[r2]
orr r1,r0,#0xD1 /*FIQMODE|NOINT*/
msr cpsr,r1 /*FIQMode*/
ldr r2,=FIQStack
ldr sp,[r2]
bic r0,r0,#0xDF /*MODEMASK|NOINT*/
orr r1,r0,#0x13
msr cpsr,r1 /*SVCMode*/
ldr r2,=SVCStack
ldr sp,[r2]
/*USER mode is not initialized.*/
mov pc,lr /*The LR register may be not valid for the mode changes.*/
/*****************************************************
* The function for entering power down mode *
*****************************************************/
/*void EnterPWDN(int CLKCON)*/
EnterPWDN:
mov r2,r0 /*r0=CLKCON*/
ldr r0,=REFRESH
ldr r3,[r0]
mov r1, r3
orr r1, r1, #0x400000 /*self-refresh enable*/
str r1, [r0]
nop /*Wait until self-refresh is issued. May not be needed.*/
nop /*If the other bus master holds the bus, ...*/
nop /* mov r0, r0*/
nop
nop
nop
nop
/*enter POWERDN mode*/
ldr r0,=CLKCON
str r2,[r0]
/*wait until enter SL_IDLE,STOP mode and until wake-up*/
mov r0,#0xff
B0: subs r0,r0,#1
bne B0
/*exit from DRAM/SDRAM self refresh mode.*/
ldr r0,=REFRESH
str r3,[r0]
mov pc,lr
SMRDATA:
/******************************************************************
* Memory configuration has to be optimized for best performance *
* The following parameter is not optimized. *
******************************************************************/
/**** memory access cycle parameter strategy ***
// 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
// 2) The memory settings,here, are made the safe parameters even at 66Mhz.
// 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
// 4) DRAM refresh rate is for 40Mhz. */
.long 0x11110090 /*Bank0=OM[1:0], Bank1~Bank7=16bit, bank2=8bit*/
.long 0x600 /*GCS0*/
.long 0x7bc0 /*GCS1*/
.long 0x7fc0 /*GCS2*/
.long 0x7ffc /*GCS3*/
.long 0x7ffc /*GCS4*/
.long 0x7ffc /*GCS5*/
.long 0x18000 /*GCS6*/
.long 0x18000 /*GCS7*/
.long 0x820591 /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/
.long 0x16 /*SCLK power mode, BANKSIZE 32M/32M*/
.long 0x20 /*MRSR6 CL=2clk*/
.long 0x20 /*MRSR7*/
UserStack: .word 0xc7ffa00
SVCStack: .word 0xc7ffb00
UndefStack: .word 0xc7ffc00
AbortStack: .word 0xc7ffd00
IRQStack: .word 0xc7ffe00
FIQStack: .word 0xc7fff00
HandleReset: .word 0xc7fff00
HandleUndef: .word 0xc7fff04
HandleSWI: .word 0xc7fff08
HandlePabort: .word 0xc7fff0c
HandleDabort: .word 0xc7fff10
HandleReserved: .word 0xc7fff14
HandleIRQ: .word 0xc7fff18
HandleFIQ: .word 0xc7fff1c
HandleADC: .word 0xc7fff20
HandleRTC: .word 0xc7fff24
HandleUTXD1: .word 0xc7fff28
HandleUTXD0: .word 0xc7fff2c
HandleSIO: .word 0xc7fff30
HandleIIC: .word 0xc7fff34
HandleURXD1: .word 0xc7fff38
HandleURXD0: .word 0xc7fff3c
HandleTIMER5: .word 0xc7fff40
HandleTIMER4: .word 0xc7fff44
HandleTIMER3: .word 0xc7fff48
HandleTIMER2: .word 0xc7fff4c
HandleTIMER1: .word 0xc7fff50
HandleTIMER0: .word 0xc7fff54
HandleUERR01: .word 0xc7fff58
HandleWDT: .word 0xc7fff5c
HandleBDMA1: .word 0xc7fff60
HandleBDMA0: .word 0xc7fff64
HandleZDMA1: .word 0xc7fff68
HandleZDMA0: .word 0xc7fff6c
HandleTICK: .word 0xc7fff70
HandleEINT4567: .word 0xc7fff74
HandleEINT3: .word 0xc7fff78
HandleEINT2: .word 0xc7fff7c
HandleEINT1: .word 0xc7fff80
HandleEINT0: .word 0xc7fff84
/* some parameters for the board */
/*Interrupt Control*/
INTPND:
.long 0x01e00004
INTMOD:
.long 0x01e00008
INTMSK:
.long 0x01e0000c
I_ISPR:
.long 0x01e00020
I_CMST:
.long 0x01e0001c
/*;Watchdog timer*/
WTCON:
.long 0x01d30000
/*;Clock Controller*/
PLLCON:
.long 0x01d80000
CLKCON:
.long 0x01d80004
LOCKTIME:
.long 0x01d8000c
/*;Memory Controller*/
REFRESH:
.long 0x01c80024
/*;Pre-defined constants*/
USERMODE:
.long 0x10
FIQMODE:
.long 0x11
IRQMODE:
.long 0x12
SVCMODE:
.long 0x13
ABORTMODE:
.long 0x17
UNDEFMODE:
.long 0x1b
MODEMASK:
.long 0x1f
NOINT:
.long 0xc0
_ISR_STARTADDRESS:
.long 0xc7fff00 /*GCS6:64M DRAM/SDRAM*/
PLLCLK:
.long 40000000
PLLCON_DAT:
.long ((2 << 0) + (3 << 4) +( 0x48<< 12))TICK: .long (0x1<<20)
MASKALL:
.long 0x07ffffff
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