cpu_init.c

基于msp430单片机的SD卡读写驱动

//#define  OS_CPU_GLOBALS
#include    <msp430xG46x.h>
#include "hal_hardware_board.h"

#ifndef NULL
#define NULL 0
#endif



#define nop() asm("NOP")

//#define INT16U unsigned int
//#define INT8U  unsigned char

int SCLK_init(void)
{
  volatile INT16U i;
  _BIS_SR(SCG0+OSCOFF+SCG1);   //turn off DCO and FLL+
  //SCFQCTL   &=~SCFQ_M; //enable modulation
  nop();
  //SCFI0   |=FN_4+FLLD_1;  //DCO range fDCOCLK =   1.4-12MHz
  //nop();
  //FLL_CTL0    |= XCAP18PF;  //XIN Cap = XOUT Cap = 18pf
  nop();
 // FLL_CTL1    |=FLL_DIV_8;   // ALCK/8
  nop();
  FLL_CTL1    &=~XT2OFF; //turn on xt2  fxt2=8M

   do
  {
    IFG1 &= ~OFIFG;                         // Clear oscillator fault flag
    for (i = 50000; i; i--);                // Delay
  }while((IFG1&OFIFG));
  nop();
  FLL_CTL1    |=SELM1;
  FLL_CTL1    |=SELM_XT2+SELS;   //select XT2 as the MCLK and SMCLK
  nop();
  return(0);
}



int IO_init(void)
{

  P1DIR |=BIT5;
  /*
  P1IE |= 0x0D;                            
  P1IES = 0x0D;
  P1IFG &= ~0x0D;                        
  */
  P2DIR |=0xff;
  P3SEL |=BIT1+BIT2;  
  P3DIR |=BIT0+BIT4+BIT5+BIT6;
  P4SEL |=BIT3+BIT4+BIT5+BIT6+BIT7;
  P4DIR |=BIT2;
  P5DIR |=BIT2+BIT3+BIT5+BIT6+BIT7;
  P6SEL |=BIT3+BIT4+BIT5; 
  P7DIR |=BIT2+BIT3+BIT4+BIT5+BIT6+BIT7;
  P8DIR |=BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT7;
  
  //P9DIR |=0xff;
  //P10DIR |=0xff;
  PBDIR |= 0xffff;
  
  return(0);
}


int UART_init(void)
{
  /*
  //SPI 8bit master
  U1CTL |=SWRST;
  nop();
  U1CTL |=CHAR+SYNC+MM; //8-bit master spi mode
  U1TCTL  |=SSEL1+STC+CKPH;    //baud rate generated by SMCLK(8M)
  U1BR0 =0X02;//0x04;        //BAUD RATE =SMCLK/8   1Mhz?
  U1BR1 =0x00;
  U1MCTL  =0x00;
  ME2 |=USPIE1;
  U1CTL &=~SWRST;
  IFG2  &=~(UTXIFG1+URXIFG1); //clear interrupt flags
  */
  //UART 8N1
  UCA0CTL1  |= UCSWRST;
  nop();
  UCA0CTL1  |=UCSSEL1;  //baud rate generated by SMCLK(8M)
  //UCA0CTL0  |=UCMSB;    //MSB first, uart mode, 8N1

  /*baud rate=9600 (BR0,BR1)=(0x41,0x03)  UCBRSX=0X02     **
  **baud rate=57600  (BR0,BR1)=(0X8A,0X00)  UCBRSX=0X07   **
  **baud rate=1M    (BR0,BR1)=(0X08,0X00)   UCBRSX=0X00   **
  */
  UCA0BR0 =0x71;  //N=SMCLK/BAUD  UCA0BR0+UCA0BR1*256=INT(N)
  UCA0BR1 =0x02;
  UCA0MCTL  =0x00;      //modulation  UCBRSX=round((N-int(N)*8))
//
  IFG2  &=~UCA0RXIFG;
  UCA0CTL1  &= ~UCSWRST;
//  IE2 |=UCA0RXIE;     //enable receive interrupt
  //I2C   7-bit address master mode
  UCB0CTL1  |=UCSWRST;
  UCB0CTL0  |=UCMODE_3+UCSYNC+UCMST; //I2C master sync mode
  UCB0CTL1  |=UCSSEL_2;  //clock source SMCLK
  UCB0I2CSA =0x50;    //slave address is 0x50 AT24C256
  UCB0BR0   =0x14;//0xa0;//100K//0x14;        //fclk=SMCLK/20=400K
  UCB0BR1   =0x00;
  UCB0CTL1  &=~UCSWRST;
  IFG2  &=~UCB0RXIFG;
  
  //UCB0I2CSA =0X50;
  return(0);

}


int CPU_init(void)
{
  //_BIS_SR(GIE);   //GIE =0 disable interrupt
  nop();
  WDTCTL  =WDTPW+WDTHOLD; //turn off watchdog
  nop();
  SCLK_init();
  IO_init();
  UART_init();
  _BIS_SR(GIE);
  return(0);
}