fifo_test.vhd

常见的输入输出及存储器件（ram及fifo）vhdl实现

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--  The Free IP Project
--  VHDL Free-FIFO Core
--  (c) 2000, The Free IP Project and David Kessner
--
--  FREE IP GENERAL PUBLIC LICENSE
--  TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
--
--  1.  You may copy and distribute verbatim copies of this core, as long
--      as this file, and the other associated files, remain intact and
--      unmodified.  Modifications are outlined below.  
--  2.  You may use this core in any way, be it academic, commercial, or
--      military.  Modified or not.  
--  3.  Distribution of this core must be free of charge.  Charging is
--      allowed only for value added services.  Value added services
--      would include copying fees, modifications, customizations, and
--      inclusion in other products.
--  4.  If a modified source code is distributed, the original unmodified
--      source code must also be included (or a link to the Free IP web
--      site).  In the modified source code there must be clear
--      identification of the modified version.
--  5.  Visit the Free IP web site for additional information.
--
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

package fifotest_lib is

  component fifo_testbench
  end component;

  function random32 (din:std_logic_vector(31 downto 0))
                     return std_logic_vector;
  function random56 (din:std_logic_vector(55 downto 0))
                     return std_logic_vector;
  function random64 (din:std_logic_vector(63 downto 0))
                     return std_logic_vector;
end fifotest_lib;

                     
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.fifotest_lib.all;

package body fifotest_lib is
  function random32 (din:std_logic_vector(31 downto 0))
                     return std_logic_vector is
    variable val	:std_logic_vector (31 downto 0);
  begin
    val := (din(31) xor din(6) xor din(4) xor din(2) xor din(1)) & din(31 downto 1);
    return (val);
  end random32;

  function random56 (din:std_logic_vector(55 downto 0))
                     return std_logic_vector is
    variable val	:std_logic_vector (55 downto 0);
  begin
    val := (din(55) xor din(6) xor din(3) xor din(1)) & din(55 downto 1);
    return (val);
  end random56;

  function random64 (din:std_logic_vector(63 downto 0))
                     return std_logic_vector is
    variable val	:std_logic_vector (63 downto 0);
  begin
    val := (din(63) xor din(3) xor din(2) xor din(0)) & din(63 downto 1);
    return (val);
  end random64;

end fifotest_lib;

  
----------------------------------------------------------------------------
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.free_fifo.all;
use work.fifotest_lib.all;


entity fifo_testbench is
--  port();
end fifo_testbench;


architecture arch_fifo_testbench of fifo_testbench is
  signal wr_clk		:std_logic := '1';
  signal rd_clk		:std_logic := '1';
  signal reset		:std_logic := '1';

  signal wr_prob	:std_logic_vector (63 downto 0) := "0010100101100100100110101101100101111001101010010100110010101001";
  signal wr_data	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal rd_prob	:std_logic_vector (63 downto 0) := "1101010101010010010100101001011010100101001001010101001010100101";
  signal rd_data	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";

  signal wr_en		:std_logic := '0';
  signal rd_en		:std_logic := '0';
  signal rd_en_d	:std_logic := '0';

  signal wr_gate	:std_logic := '1';
  signal rd_gate	:std_logic := '1';

  signal dout		:std_logic_vector (15 downto 0) := "0000000000000000";
  signal full		:std_logic := '0';
  signal empty		:std_logic := '0';
begin
  reset <= '1' after 0 ns, '0' after 32 ns;  

  process (rd_clk)
  begin
    if rd_clk='1' then
--      rd_clk <= '0' after 5 ns, '1' after 10 ns;
      rd_clk <= '0' after 10 ns, '1' after 20 ns;
    end if;
  end process;

  process (wr_clk)
  begin
    if wr_clk='1' then
      wr_clk <= '0' after 5 ns, '1' after 10.01 ns;
    end if;
  end process;


  -- Generate the read and write probabilities
  process (reset, wr_clk)
  begin
    if reset='1' then
      wr_prob <= "0010100101100100100110101101100101111001101010010100110010101001";
    elsif wr_clk'event and wr_clk='1' then
      wr_prob <= random64(wr_prob);
    end if;
  end process;

  process (reset, rd_clk)
  begin
    if reset='1' then
      rd_prob <= "1010001101010110101010101010110110101010101101101010101101010101";
    elsif rd_clk'event and rd_clk='1' then
      rd_prob <= random64(rd_prob);
    end if;
  end process;
    
  wr_en <= '1' when wr_prob(63)='1' and wr_prob(23)='0' and full='0'  and wr_gate='1' else '0';
  wr_gate <= '0' after 0 ns, '1' after 100 ns;

--  rd_en <= '1' when rd_prob(63)='1' and rd_prob(23)='0' and empty='0' and rd_gate='1' else '0';
  rd_en <= '1' when rd_prob(23)='0' and empty='0' and rd_gate='1' else '0';
  rd_gate <= '0' after 0 ns, '1' after 1000 ns;

  process (reset, rd_clk)
  begin
    if reset='1' then
      rd_en_d <= '0';
    elsif rd_clk='1' and rd_clk'event then
      rd_en_d <= rd_en;
    end if;
  end process;


  -- Instantiate the FIFO
  U1: fifo_async
      generic map (data_bits => dout'high+1,
                   addr_bits => 4,
                   block_type => 0,
                   use_xilinx_patent => 0)
      port map (reset,
                wr_clk, wr_en, wr_data(wr_data'high downto wr_data'high-dout'high),
                rd_clk, rd_en, dout, full, empty);
  


  -- Generate the random write data
  process (reset, wr_clk)
  begin
    if reset='1' then
      wr_data <= "1001001000011010010010001001001001001000011110100100100100101101";
    elsif wr_clk'event and wr_clk='1' then
      if wr_en='1' then
        wr_data <= random64(wr_data);
      end if;
    end if;
  end process;


  -- Generate the random read data
  process (reset, rd_clk)
  begin
    if reset='1' then
      rd_data <= "1001001000011010010010001001001001001000011110100100100100101101";
    elsif rd_clk'event and rd_clk='1' then
      if rd_en_d='1' then
        rd_data <= random64(rd_data);
      end if;
    end if;
  end process;


  -- Verify the FIFO output
  process (reset, rd_clk)
  begin
    if rd_clk'event and rd_clk='1' then
      if rd_en_d='1' then
        if dout /= rd_data(wr_data'high downto wr_data'high-dout'high) then
          assert 1=0
            report "Simulation Ended, FIFO DOUT Mismatch!!!!!!!!!!!!!!!!!!!!!!!!!"
            severity failure;
        end if;
      end if;
    end if;
  end process;

end arch_fifo_testbench;


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