power_pcb10.17.drc

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Protel Design System Design Rule Check
PCB File : \WORK\电源电路\Power_PCB10.17.PCBDOC
Date     : 2007-10-19
Time     : 17:24:28

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=4mil) (All),(All)
Rule Violations :0

Processing Rule : Width Constraint (Min=4mil) (Max=200mil) (Preferred=10mil) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=1mil) (Max=200mil) (All)
Rule Violations :0


Violations Detected : 0
Time Elapsed        : 00:00:10