_primary.vhd

很精彩的双端口RAM应用笔记

library verilog;
use verilog.vl_types.all;
entity Doul_RAM is
    port(
        DINA            : in     vl_logic_vector(7 downto 0);
        DOUTA           : out    vl_logic_vector(7 downto 0);
        DINB            : in     vl_logic_vector(7 downto 0);
        DOUTB           : out    vl_logic_vector(7 downto 0);
        ADDRA           : in     vl_logic_vector(4 downto 0);
        ADDRB           : in     vl_logic_vector(4 downto 0);
        RWA             : in     vl_logic;
        RWB             : in     vl_logic;
        BLKA            : in     vl_logic;
        BLKB            : in     vl_logic;
        CLKA            : in     vl_logic;
        CLKB            : in     vl_logic
    );
end Doul_RAM;