_primary.vhd

来自「很精彩的双端口RAM应用笔记」· VHDL 代码 · 共 21 行

library verilog;
use verilog.vl_types.all;
entity read_wirte_ram is
    generic(
        read            : integer := 1;
        idle            : integer := 2
    );
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        ADDRA           : out    vl_logic_vector(4 downto 0);
        ADDRB           : out    vl_logic_vector(4 downto 0);
        RWA             : out    vl_logic;
        RWB             : out    vl_logic;
        BLKA            : out    vl_logic;
        BLKB            : out    vl_logic;
        CLKA            : out    vl_logic;
        CLKB            : out    vl_logic
    );
end read_wirte_ram;