_primary.vhd

来自「很精彩的双端口RAM应用笔记」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity stimulus is
    port(
        clk             : out    vl_logic;
        reset           : out    vl_logic
    );
end stimulus;