_primary.vhd

很精彩的双端口RAM应用笔记

library verilog;
use verilog.vl_types.all;
entity top is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        ADDRA           : out    vl_logic_vector(4 downto 0);
        ADDRB           : out    vl_logic_vector(4 downto 0);
        RWA             : out    vl_logic;
        RWB             : out    vl_logic;
        CLKA            : out    vl_logic;
        CLKB            : out    vl_logic;
        DOUTA           : out    vl_logic_vector(7 downto 0);
        DOUTB           : out    vl_logic_vector(7 downto 0)
    );
end top;