p9050_lib.h

adlink master board 6760 pci driver for control powerspan slave pci driver

#ifndef _P9050_LIB_H_
#define _P9050_LIB_H_

#ifdef __KERNEL__
    #include "../../../include/kdstdlib.h"
#endif //__KERNEL__
#include "../../../include/windrvr.h"
#include "../../../samples/shared/pci_regs.h"
#include "../../../samples/shared/bits.h"

#ifdef __cplusplus
extern "C" {
#endif

//////////////
#define T_P1_TI0_CTL     0x100
#define T_P1_TI0_ADDR    0x104
#define T_P1_TI1_CTL     0x110
#define T_P1_TI1_ADDR    0x114
#define T_P1_TI2_CTL     0x120
#define T_P1_TI2_ADDR    0x124
#define T_P1_TI3_CTL     0x130
#define T_P1_TI3_ADDR    0x134
#define T_P1_CONF_INFO   0x144
#define T_P1_CONF_DATA   0x148
#define T_P1_IACK        0x14C
#define T_P1_ERRCS       0x150
#define T_P1_AERR        0x154
#define T_P1_MISC_CSR    0x160
#define T_P1_ARB_CTRL    0x164

#define T_PB_SI0_CTL     0x200
#define T_PB_SI0_TADDR   0x204
#define T_PB_SI0_BADDR   0x208
#define T_PB_SI1_CTL     0x210
#define T_PB_SI1_TADDR   0x214
#define T_PB_SI1_BADDR   0x218
#define T_PB_SI2_CTL     0x220
#define T_PB_SI2_TADDR   0x224
#define T_PB_SI2_BADDR   0x228
#define T_PB_SI3_CTL     0x230
#define T_PB_SI3_TADDR   0x234
#define T_PB_SI3_BADDR   0x238
#define T_PB_SI4_CTL     0x240
#define T_PB_SI4_TADDR   0x244
#define T_PB_SI4_BADDR   0x248
#define T_PB_SI5_CTL     0x250
#define T_PB_SI5_TADDR   0x254
#define T_PB_SI5_BADDR   0x258
#define T_PB_SI6_CTL     0x260
#define T_PB_SI6_TADDR   0x264
#define T_PB_SI6_BADDR   0x268
#define T_PB_SI7_CTL     0x270
#define T_PB_SI7_TADDR   0x274
#define T_PB_SI7_BADDR   0x278
#define T_PB_REG_BADDR   0x280
#define T_PB_CONF_INFO   0x290
#define T_PB_CONF_DATA   0x294
#define T_PB_P1_IACK     0x2A0
#define T_PB_P2_IACK     0x2A4
#define T_PB_ERRCS       0x2B0
#define T_PB_AERR        0x2B4
#define T_PB_MISC_CSR    0x2C0
#define T_PB_ARB_CTRL    0x2D0

#define T_DMA0_SRC_ADDR  0x304
#define T_DMA0_DST_ADDR  0x30C
#define T_DMA0_TCR       0x314
#define T_DMA0_CPP       0x31C
#define T_DMA0_GCSR      0x320
#define T_DMA0_ATTR      0x324
#define T_DMA1_SRC_ADDR  0x334
#define T_DMA1_DST_ADDR  0x33C
#define T_DMA1_TCR       0x344
#define T_DMA1_CPP       0x34C
#define T_DMA1_GCSR      0x350
#define T_DMA1_ATTR      0x354
#define T_DMA2_SRC_ADDR  0x364
#define T_DMA2_DST_ADDR  0x36C
#define T_DMA2_TCR       0x374
#define T_DMA2_CPP       0x37C
#define T_DMA2_GCSR      0x380
#define T_DMA2_ATTR      0x384
#define T_DMA3_SRC_ADDR  0x394
#define T_DMA3_DST_ADDR  0x39C
#define T_DMA3_TCR       0x3A4
#define T_DMA3_CPP       0x3AC
#define T_DMA3_GCSR      0x3B0
#define T_DMA3_ATTR      0x3B4

#define T_MISC_CSR       0x400
#define T_CLOCK_CTL      0x404
#define T_I2C_CSR        0x408
#define T_RST_CSR        0x40C
#define T_ISR0           0x410
#define T_ISR1           0x414
#define T_IER0           0x418
#define T_IER1           0x41C
#define T_IMR_MBOX       0x420
#define T_IMR_DB         0x424
#define T_IMR_DMA        0x428
#define T_IMR_HW         0x42C
#define T_IMR_P1         0x430
#define T_IMR_P2         0x434
#define T_IMR_PB         0x438
#define T_IMR2_PB        0x43C
#define T_IMR_MISC       0x440
#define T_IDR            0x444

#define T_MBOX0          0x450
#define T_MBOX1          0x454
#define T_MBOX2          0x458
#define T_MBOX3          0x45C
#define T_MBOX4          0x460
#define T_MBOX5          0x464
#define T_MBOX6          0x468
#define T_MBOX7          0x46C
#define T_SEMA0          0x470
#define T_SEMA1          0x474

#define T_PCI_TI2O_CTL   0x500
#define T_PCI_TI2O_TADDR 0x504
#define T_I2O_CSR        0x508
#define T_I2O_QUEUE_BS   0x50C
#define T_IFL_BOT        0x510
#define T_IFL_TOP        0x514
#define T_IFL_TOP_INC    0x518
#define T_IPL_BOT        0x51C
#define T_IPL_BOT_INC    0x520
#define T_IPL_TOP        0x524
#define T_OFL_BOT        0x528
#define T_OFL_BOT_INC    0x52C
#define T_OFL_TOP        0x530
#define T_OPL_BOT        0x534
#define T_OPL_TOP        0x538
#define T_OPL_TOP_INC    0x53C
#define T_HOST_OIO       0x540
#define T_HOST_OIA       0x544
#define T_IOP_OI         0x548
#define T_IOP_OI_INC     0x54C

/////////////



// PLX register definitions 
enum {
    P9050_LAS0RR  = 0x00,
    P9050_LAS1RR  = 0x04,
    P9050_LAS2RR  = 0x08,
    P9050_LAS3RR  = 0x0c,
    P9050_EROMRR  = 0x10,
    P9050_LAS0BA  = 0x14,
    P9050_LAS1BA  = 0x18,
    P9050_LAS2BA  = 0x1c,
    P9050_LAS3BA  = 0x20,
    P9050_EROMBA  = 0x24,
    P9050_LAS0BRD = 0x28,
    P9050_LAS1BRD = 0x2c,
    P9050_LAS2BRD = 0x30,
    P9050_LAS3BRD = 0x34,
    P9050_EROMBRD = 0x38,
    P9050_CS0BASE = 0x3c,
    P9050_CS1BASE = 0x40,
    P9050_CS2BASE = 0x44,
    P9050_CS3BASE = 0x48,
    P9050_INTCSR  = 0x4c,
    P9050_CNTRL   = 0x50,
    
    
    P9054_INTCSR  = 0x68,  
    
    P9054_DMAMODE   = 0x80,
    P9054_DMAPADR   = 0x84,
    P9054_DMALADR   = 0x88,
    P9054_DMASIZ    = 0x8c,
    P9054_DMADPR    = 0x90,
    P9054_DMACSR    = 0xa8,
    
    P9054_DMAMODE1  = 0x94,
    P9054_DMAPADR1  = 0x98,
    P9054_DMALADR1  = 0x9c,
    P9054_DMASIZ1   = 0xa0,
    P9054_DMADPR1   = 0xa4,
    P9054_DMACSR1   = 0xa9   
};

typedef enum
{
    P9050_MODE_BYTE   = 0,
    P9050_MODE_WORD   = 1,
    P9050_MODE_DWORD  = 2
} P9050_MODE;

typedef enum
{
    P9050_ADDR_REG     = AD_PCI_BAR0 + 1,// added "+1" by pgn
    P9050_ADDR_REG_IO  = AD_PCI_BAR1,
    P9050_ADDR_SPACE0  = AD_PCI_BAR2,
    P9050_ADDR_SPACE1  = AD_PCI_BAR3,
    P9050_ADDR_SPACE2  = AD_PCI_BAR4,
    P9050_ADDR_SPACE3  = AD_PCI_BAR5,
    P9050_ADDR_EPROM   = AD_PCI_BAR_EPROM,
} P9050_ADDR;


enum { P9050_RANGE_REG = 0x00000080 };

typedef struct P9050_STRUCT *P9050_HANDLE;
typedef P9050_HANDLE P9050HANDLE;

typedef struct
{
    DWORD dwCounter;   // number of interrupts received
    DWORD dwLost;      // number of interrupts not yet dealt with
    BOOL fStopped;     // was interrupt disabled during wait
    DWORD dwStatusReg; // value of status register when interrupt occurred
} P9050_INT_RESULT;

typedef void (WINAPI *P9050_INT_HANDLER)( P9050_HANDLE hPlx, P9050_INT_RESULT *intResult);

// options for PLX_Open
enum { P9050_OPEN_FIX_BIT7 =   0x1 };

DWORD P9050_CountCards (DWORD dwVendorID, DWORD dwDeviceID);
BOOL P9050_Open (P9050_HANDLE *phPlx, DWORD dwVendorID, DWORD dwDeviceID, DWORD nCardNum, DWORD options);
void P9050_Close (P9050_HANDLE hPlx);
BOOL P9050_IsAddrSpaceActive(P9050_HANDLE hPlx, P9050_ADDR addrSpace);
void P9050_GetPciSlot(P9050_HANDLE hPlx, WD_PCI_SLOT *pPciSlot);

void P9050_ReadWriteBlock (P9050_HANDLE hPlx, DWORD dwLocalAddr, PVOID buf, 
                    DWORD dwBytes, BOOL fIsRead, P9050_ADDR addrSpace, P9050_MODE mode);
void P9050_ReadBlock (P9050_HANDLE hPlx, DWORD dwLocalAddr, PVOID buf, 
                    DWORD dwBytes, P9050_ADDR addrSpace, P9050_MODE mode);
void P9050_WriteBlock (P9050_HANDLE hPlx, DWORD dwLocalAddr, PVOID buf, 
                    DWORD dwBytes, P9050_ADDR addrSpace, P9050_MODE mode);
BYTE P9050_ReadByte (P9050_HANDLE hPlx, P9050_ADDR addrSpace, DWORD dwLocalAddr);
void P9050_WriteByte (P9050_HANDLE hPlx, P9050_ADDR addrSpace, DWORD dwLocalAddr, BYTE data);
WORD P9050_ReadWord (P9050_HANDLE hPlx, P9050_ADDR addrSpace, DWORD dwLocalAddr);
void P9050_WriteWord (P9050_HANDLE hPlx, P9050_ADDR addrSpace, DWORD dwLocalAddr, WORD data);
DWORD P9050_ReadDWord (P9050_HANDLE hPlx, P9050_ADDR addrSpace, DWORD dwLocalAddr);
void P9050_WriteDWord (P9050_HANDLE hPlx, P9050_ADDR addrSpace, DWORD dwLocalAddr, DWORD data);

void P9050_ReadWriteSpaceBlock (P9050_HANDLE hPlx, DWORD dwOffset, PVOID buf, 
                    DWORD dwBytes, BOOL fIsRead, P9050_ADDR addrSpace, P9050_MODE mode);
void P9050_ReadSpaceBlock (P9050_HANDLE hPlx, DWORD dwOffset, PVOID buf, 
                    DWORD dwBytes, P9050_ADDR addrSpace, P9050_MODE mode);
void P9050_WriteSpaceBlock (P9050_HANDLE hPlx, DWORD dwOffset, PVOID buf, 
                    DWORD dwBytes, P9050_ADDR addrSpace, P9050_MODE mode);
BYTE P9050_ReadSpaceByte (P9050_HANDLE hPlx, P9050_ADDR addrSpace, DWORD dwOffset);
void P9050_WriteSpaceByte (P9050_HANDLE hPlx, P9050_ADDR addrSpace, DWORD dwOffset, BYTE data);
WORD P9050_ReadSpaceWord (P9050_HANDLE hPlx, P9050_ADDR addrSpace, DWORD dwOffset);
void P9050_WriteSpaceWord (P9050_HANDLE hPlx, P9050_ADDR addrSpace, DWORD dwOffset, WORD data);
DWORD P9050_ReadSpaceDWord (P9050_HANDLE hPlx, P9050_ADDR addrSpace, DWORD dwOffset);
void P9050_WriteSpaceDWord (P9050_HANDLE hPlx, P9050_ADDR addrSpace, DWORD dwOffset, DWORD data);

BOOL P9050_IntIsEnabled (P9050_HANDLE hPlx);
BOOL P9050_IntEnable (P9050_HANDLE hPlx, P9050_INT_HANDLER funcIntHandler);
void P9050_IntDisable (P9050_HANDLE hPlx, P9050_INT_HANDLER funcIntHandler);
void P9050_IntSet (P9050_HANDLE hPlx);
void P9050_IntClear (P9050_HANDLE hPlx);

DWORD P9050_ReadReg (P9050_HANDLE hPlx, DWORD dwReg);
void P9050_WriteReg (P9050_HANDLE hPlx, DWORD dwReg, DWORD dwData);

BOOL P9050_EEPROMReadWord(P9050_HANDLE hPlx, DWORD dwOffset, PWORD pwData);
BOOL P9050_EEPROMWriteWord(P9050_HANDLE hPlx, DWORD dwOffset, WORD wData);
BOOL P9050_EEPROMReadDWord(P9050_HANDLE hPlx, DWORD dwOffset, PDWORD pdwData);
BOOL P9050_EEPROMWriteDWord(P9050_HANDLE hPlx, DWORD dwOffset, DWORD dwData);
BOOL P9050_EEPROMValid(P9050_HANDLE hPlx);

DWORD P9050_ReadPCIReg(P9050_HANDLE hPlx, DWORD dwReg);
void P9050_WritePCIReg(P9050_HANDLE hPlx, DWORD dwReg, DWORD dwData);

// this string is set to an error message, if one occurs
extern CHAR P9050_ErrorString[];

#ifdef __cplusplus
}
#endif

#endif