📄 pspan_lib.h
字号:
#ifndef _PSPAN_LIB_H_
#define _PSPAN_LIB_H_
#ifdef __KERNEL__
#include "../../../include/kdstdlib.h"
#endif //__KERNEL__
#include "../../../include/windrvr.h"
#include "../../../samples/shared/pci_regs.h"
#include "../../../samples/shared/bits.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(UCHAR)
#define UCHAR unsigned char
#endif
#if !defined(UINT)
#define UINT unsigned int
#endif
#define EEPROM_SIZE 0x100
///////////////////////////////////////////
// PspanII register definitions
#define T_P1_TI0_CTL 0x100
#define T_P1_TI0_ADDR 0x104
#define T_P1_TI1_CTL 0x110
#define T_P1_TI1_ADDR 0x114
#define T_P1_TI2_CTL 0x120
#define T_P1_TI2_ADDR 0x124
#define T_P1_TI3_CTL 0x130
#define T_P1_TI3_ADDR 0x134
#define T_P1_CONF_INFO 0x144
#define T_P1_CONF_DATA 0x148
#define T_P1_IACK 0x14C
#define T_P1_ERRCS 0x150
#define T_P1_AERR 0x154
#define T_P1_MISC_CSR 0x160
#define T_P1_ARB_CTRL 0x164
#define T_PB_SI0_CTL 0x200
#define T_PB_SI0_TADDR 0x204
#define T_PB_SI0_BADDR 0x208
#define T_PB_SI1_CTL 0x210
#define T_PB_SI1_TADDR 0x214
#define T_PB_SI1_BADDR 0x218
#define T_PB_SI2_CTL 0x220
#define T_PB_SI2_TADDR 0x224
#define T_PB_SI2_BADDR 0x228
#define T_PB_SI3_CTL 0x230
#define T_PB_SI3_TADDR 0x234
#define T_PB_SI3_BADDR 0x238
#define T_PB_SI4_CTL 0x240
#define T_PB_SI4_TADDR 0x244
#define T_PB_SI4_BADDR 0x248
#define T_PB_SI5_CTL 0x250
#define T_PB_SI5_TADDR 0x254
#define T_PB_SI5_BADDR 0x258
#define T_PB_SI6_CTL 0x260
#define T_PB_SI6_TADDR 0x264
#define T_PB_SI6_BADDR 0x268
#define T_PB_SI7_CTL 0x270
#define T_PB_SI7_TADDR 0x274
#define T_PB_SI7_BADDR 0x278
#define T_PB_REG_BADDR 0x280
#define T_PB_CONF_INFO 0x290
#define T_PB_CONF_DATA 0x294
#define T_PB_P1_IACK 0x2A0
#define T_PB_P2_IACK 0x2A4
#define T_PB_ERRCS 0x2B0
#define T_PB_AERR 0x2B4
#define T_PB_MISC_CSR 0x2C0
#define T_PB_ARB_CTRL 0x2D0
#define T_DMA0_SRC_ADDR 0x304
#define T_DMA0_DST_ADDR 0x30C
#define T_DMA0_TCR 0x314
#define T_DMA0_CPP 0x31C
#define T_DMA0_GCSR 0x320
#define T_DMA0_ATTR 0x324
#define T_DMA1_SRC_ADDR 0x334
#define T_DMA1_DST_ADDR 0x33C
#define T_DMA1_TCR 0x344
#define T_DMA1_CPP 0x34C
#define T_DMA1_GCSR 0x350
#define T_DMA1_ATTR 0x354
#define T_DMA2_SRC_ADDR 0x364
#define T_DMA2_DST_ADDR 0x36C
#define T_DMA2_TCR 0x374
#define T_DMA2_CPP 0x37C
#define T_DMA2_GCSR 0x380
#define T_DMA2_ATTR 0x384
#define T_DMA3_SRC_ADDR 0x394
#define T_DMA3_DST_ADDR 0x39C
#define T_DMA3_TCR 0x3A4
#define T_DMA3_CPP 0x3AC
#define T_DMA3_GCSR 0x3B0
#define T_DMA3_ATTR 0x3B4
#define T_MISC_CSR 0x400
#define T_CLOCK_CTL 0x404
#define T_I2C_CSR 0x408
#define T_RST_CSR 0x40C
#define T_ISR0 0x410
#define T_ISR1 0x414
#define T_IER0 0x418
#define T_IER1 0x41C
#define T_IMR_MBOX 0x420
#define T_IMR_DB 0x424
#define T_IMR_DMA 0x428
#define T_IMR_HW 0x42C
#define T_IMR_P1 0x430
#define T_IMR_P2 0x434
#define T_IMR_PB 0x438
#define T_IMR2_PB 0x43C
#define T_IMR_MISC 0x440
#define T_IDR 0x444
#define T_MBOX0 0x450
#define T_MBOX1 0x454
#define T_MBOX2 0x458
#define T_MBOX3 0x45C
#define T_MBOX4 0x460
#define T_MBOX5 0x464
#define T_MBOX6 0x468
#define T_MBOX7 0x46C
#define T_SEMA0 0x470
#define T_SEMA1 0x474
#define T_PCI_TI2O_CTL 0x500
#define T_PCI_TI2O_TADDR 0x504
#define T_I2O_CSR 0x508
#define T_I2O_QUEUE_BS 0x50C
#define T_IFL_BOT 0x510
#define T_IFL_TOP 0x514
#define T_IFL_TOP_INC 0x518
#define T_IPL_BOT 0x51C
#define T_IPL_BOT_INC 0x520
#define T_IPL_TOP 0x524
#define T_OFL_BOT 0x528
#define T_OFL_BOT_INC 0x52C
#define T_OFL_TOP 0x530
#define T_OPL_BOT 0x534
#define T_OPL_TOP 0x538
#define T_OPL_TOP_INC 0x53C
#define T_HOST_OIO 0x540
#define T_HOST_OIA 0x544
#define T_IOP_OI 0x548
#define T_IOP_OI_INC 0x54C
/////////////////////////////////////////////////////////////////////////////////////////
// DMA process begin
#define PB 0
#define PCI1 1
#define PCI2 2
#define BIG_ENDIAN 0
#define LITTLE_ENDIAN 1
#define PPC_LITTLE_ENDIAN 2
#define DMAx_TCR_SRC_PORT_P1_VAL 0x00000000
#define DMAx_TCR_SRC_PORT_P2_VAL 0x40000000
#define DMAx_TCR_SRC_PORT_PB_VAL 0x80000000
#define DMAx_TCR_DST_PORT_P1_VAL 0x00000000
#define DMAx_TCR_DST_PORT_P2_VAL 0x10000000
#define DMAx_TCR_DST_PORT_PB_VAL 0x20000000
#define DMAx_TCR_BC_MASK 0x00ffffff
#define DMAx_CPP_NCP_MASK 0xffffffe0
#define DMAx_CPP_LAST_MASK 0x00000001
#define DMAx_GCR_GO_MASK 0x80000000
#define DMAx_GCR_CHAIN_MASK 0x40000000
#define DMAx_GCR_DACT_MASK 0x00800000
#define DMAx_GCR_P1_ERR_MASK 0x00002000
#define DMAx_GCR_P2_ERR_MASK 0x00001000
#define DMAx_GCR_PB_ERR_MASK 0x00000800
#define DMAx_GCR_STOP_MASK 0x00000400
#define DMAx_GCR_HALT_MASK 0x00000200
#define DMAx_GCR_DONE_MASK 0x00000100
#define DMAx_ATTR_CPA_PORT_P1_VAL 0x00000000
#define DMAx_ATTR_CPA_PORT_P2_VAL 0x40000000
#define DMAx_ATTR_CPA_PORT_PB_VAL 0x80000000
#define DMAx_ATTR_GBL_MASK 0x10000000
#define DMAx_ATTR_CI_MASK 0x08000000
#define DMAx_ATTR_CPA_PORT_MASK 0xc0000000
struct PowerSpanCmdPktDef {
unsigned long Reserved00;
unsigned long DMAx_SRC_ADDR;
unsigned long Reserved08;
unsigned long DMAx_DST_ADDR;
unsigned long Reserved10;
unsigned long DMAx_TCR;
unsigned long Reserved18;
unsigned long DMAx_CPP;
};
#define NET_SWAP16(var) var \
//(((((WORD)(var)) >> 8) & 0x00FF) | ((((WORD)(var)) << 8) & 0xFF00))
#define NET_SWAP32(lvar) lvar \
//((DWORD)(NET_SWAP16(((DWORD)(lvar) >> 16) & 0x0000FFFF) | \
// (NET_SWAP16((DWORD)(lvar) & 0x0000FFFF) << 16)))
// DMA process end
///////////////////////////////////////////////////////////////////
// PspanII register definitions
enum {
PSPAN_LAS0RR = 0x00,
PSPAN_LAS1RR = 0x04,
PSPAN_LAS2RR = 0x08,
PSPAN_LAS3RR = 0x0c,
PSPAN_EROMRR = 0x10,
PSPAN_LAS0BA = 0x14,
PSPAN_LAS1BA = 0x18,
PSPAN_LAS2BA = 0x1c,
PSPAN_LAS3BA = 0x20,
PSPAN_EROMBA = 0x24,
PSPAN_LAS0BRD = 0x28,
PSPAN_LAS1BRD = 0x2c,
PSPAN_LAS2BRD = 0x30,
PSPAN_LAS3BRD = 0x34,
PSPAN_EROMBRD = 0x38,
PSPAN_CS0BASE = 0x3c,
PSPAN_CS1BASE = 0x40,
PSPAN_CS2BASE = 0x44,
PSPAN_CS3BASE = 0x48,
PSPAN_INTCSR = 0x4c,
PSPAN_CNTRL = 0x50
};
typedef enum
{
PSPAN_MODE_BYTE = 0,
PSPAN_MODE_WORD = 1,
PSPAN_MODE_DWORD = 2
} PSPAN_MODE;
typedef enum
{
PSPAN_ADDR_REG = AD_PCI_BAR0 + 1,// added "+1" by pgn
PSPAN_ADDR_REG_IO = AD_PCI_BAR1,
PSPAN_ADDR_SPACE0 = AD_PCI_BAR2,
PSPAN_ADDR_SPACE1 = AD_PCI_BAR3,
PSPAN_ADDR_SPACE2 = AD_PCI_BAR4,
PSPAN_ADDR_SPACE3 = AD_PCI_BAR5,
PSPAN_ADDR_EPROM = AD_PCI_BAR_EPROM,
} PSPAN_ADDR;
enum { PSPAN_RANGE_REG = 0x00000080 };
typedef struct PSPAN_STRUCT *PSPAN_HANDLE;
typedef PSPAN_HANDLE PSPANHANDLE;
typedef struct
{
DWORD dwCounter; // number of interrupts received
DWORD dwLost; // number of interrupts not yet dealt with
BOOL fStopped; // was interrupt disabled during wait
DWORD dwStatusReg; // value of status register when interrupt occurred
} PSPAN_INT_RESULT;
//typedef void (WINAPI *PSPAN_INT_HANDLER)( PSPAN_HANDLE hPlx/*, PSPAN_INT_RESULT *intResult*/);
typedef void (WINAPI *PSPAN_INT_HANDLER)( PSPAN_HANDLE hPlx);
// options for PSPAN_Open
enum { PSPAN_OPEN_FIX_BIT7 = 0x1 };
DWORD PSPAN_CountCards (DWORD dwVendorID, DWORD dwDeviceID);
BOOL PSPAN_Open (PSPAN_HANDLE *phPlx, DWORD dwVendorID, DWORD dwDeviceID, DWORD nCardNum, DWORD options);
void PSPAN_Close (PSPAN_HANDLE hPlx);
BOOL PSPAN_IsAddrSpaceActive(PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace);
void PSPAN_GetPciSlot(PSPAN_HANDLE hPlx, WD_PCI_SLOT *pPciSlot);
void PSPAN_ReadWriteBlock (PSPAN_HANDLE hPlx, DWORD dwLocalAddr, PVOID buf,
DWORD dwBytes, BOOL fIsRead, PSPAN_ADDR addrSpace, PSPAN_MODE mode);
void PSPAN_ReadBlock (PSPAN_HANDLE hPlx, DWORD dwLocalAddr, PVOID buf,
DWORD dwBytes, PSPAN_ADDR addrSpace, PSPAN_MODE mode);
void PSPAN_WriteBlock (PSPAN_HANDLE hPlx, DWORD dwLocalAddr, PVOID buf,
DWORD dwBytes, PSPAN_ADDR addrSpace, PSPAN_MODE mode);
BYTE PSPAN_ReadByte (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwLocalAddr);
void PSPAN_WriteByte (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwLocalAddr, BYTE data);
WORD PSPAN_ReadWord (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwLocalAddr);
void PSPAN_WriteWord (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwLocalAddr, WORD data);
DWORD PSPAN_ReadDWord (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwLocalAddr);
void PSPAN_WriteDWord (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwLocalAddr, DWORD data);
void PSPAN_ReadWriteSpaceBlock (PSPAN_HANDLE hPlx, DWORD dwOffset, PVOID buf,
DWORD dwBytes, BOOL fIsRead, PSPAN_ADDR addrSpace, PSPAN_MODE mode);
void PSPAN_ReadSpaceBlock (PSPAN_HANDLE hPlx, DWORD dwOffset, PVOID buf,
DWORD dwBytes, PSPAN_ADDR addrSpace, PSPAN_MODE mode);
void PSPAN_WriteSpaceBlock (PSPAN_HANDLE hPlx, DWORD dwOffset, PVOID buf,
DWORD dwBytes, PSPAN_ADDR addrSpace, PSPAN_MODE mode);
BYTE PSPAN_ReadSpaceByte (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwOffset);
void PSPAN_WriteSpaceByte (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwOffset, BYTE data);
WORD PSPAN_ReadSpaceWord (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwOffset);
void PSPAN_WriteSpaceWord (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwOffset, WORD data);
DWORD PSPAN_ReadSpaceDWord (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwOffset);
void PSPAN_WriteSpaceDWord (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwOffset, DWORD data);
BOOL PSPAN_IntIsEnabled (PSPAN_HANDLE hPlx);
BOOL PSPAN_IntEnable (PSPAN_HANDLE hPlx, PSPAN_INT_HANDLER funcIntHandler);
void PSPAN_IntDisable (PSPAN_HANDLE hPlx, PSPAN_INT_HANDLER funcIntHandler);
void PSPAN_IntSet (PSPAN_HANDLE hPlx);
void PSPAN_IntClear (PSPAN_HANDLE hPlx);
DWORD PSPAN_ReadReg (PSPAN_HANDLE hPlx, DWORD dwReg);
void PSPAN_WriteReg (PSPAN_HANDLE hPlx, DWORD dwReg, DWORD dwData);
void PSPAN_SetMode (PSPAN_HANDLE hPlx, PSPAN_ADDR addrSpace, DWORD dwLocalAddr);
UCHAR PSPAN_ProgramEeprom(PSPAN_HANDLE hPlx, unsigned char * buf, unsigned char size);
UCHAR PSPAN_ReadEeprom(PSPAN_HANDLE hPlx, unsigned char *buf);
void PSPAN_EepromByteWrite(PSPAN_HANDLE hPlx, unsigned char addr, unsigned char data);
UCHAR PSPAN_EepromByteRead(PSPAN_HANDLE hPlx, unsigned char addr);
void PSPAN_EepromWordWrite(PSPAN_HANDLE hPlx, unsigned char addr, unsigned short data);
UINT PSPAN_EepromWordRead(PSPAN_HANDLE hPlx, unsigned char addr);
DWORD PSPAN_ReadPCIReg(PSPAN_HANDLE hPlx, DWORD dwReg);
void PSPAN_WritePCIReg(PSPAN_HANDLE hPlx, DWORD dwReg, DWORD dwData);
// this string is set to an error message, if one occurs
extern CHAR PSPAN_ErrorString[];
///////////////////////////////////////////////////////////////
// DMA begin
int PSPAN_directModeDMA(PSPAN_HANDLE hPlx,
unsigned long src_addr,
unsigned long dst_addr,
unsigned long src_port,
unsigned long dst_port,
unsigned long byte_count,
unsigned long channel );
int PSPAN_isDMADone(PSPAN_HANDLE hPlx,unsigned long channel );
int PSPAN_checkDMAStatus(PSPAN_HANDLE hPlx, unsigned long channel );
int PSPAN_createCommandPacket( struct PowerSpanCmdPktDef *p_PowerSpanCmdPktDef,
unsigned long src_addr,
unsigned long dst_addr,
unsigned long src_port,
unsigned long dst_port,
unsigned long byte_count,
struct PowerSpanCmdPktDef* next_cmd_pkt_ptr,
unsigned long last );
int PSPAN_linkedListDMA( PSPAN_HANDLE hPlx,
struct PowerSpanCmdPktDef *cmd_ppkt,
unsigned long cmd_pkt_port,
unsigned long channel);
void PSPAN_configureDMAInterrupts(PSPAN_HANDLE hPlx,unsigned long channel);
#define PCI_SWAP16(var) \
( ((((WORD)(var)) >> 8) & 0x00FF) | ((((WORD)(var)) << 8) & 0xFF00) )
#define PCI_SWAP32(lvar) \
( (DWORD)(PCI_SWAP16(((DWORD)(lvar) >> 16) & 0x0000FFFF) | \
(PCI_SWAP16((DWORD)(lvar) & 0x0000FFFF) << 16)) )
// DMA end
////////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#endif
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -