📄 io_map.h
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} Bits;
} ADCCVLSTR;
#define ADCCVL _ADCCV.Overlap_STR.ADCCVLSTR.Byte
#define ADCCVL_ADCV0 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV0
#define ADCCVL_ADCV1 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV1
#define ADCCVL_ADCV2 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV2
#define ADCCVL_ADCV3 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV3
#define ADCCVL_ADCV4 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV4
#define ADCCVL_ADCV5 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV5
#define ADCCVL_ADCV6 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV6
#define ADCCVL_ADCV7 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV7
#define ADCCVL_ADCV0_MASK 0x01
#define ADCCVL_ADCV1_MASK 0x02
#define ADCCVL_ADCV2_MASK 0x04
#define ADCCVL_ADCV3_MASK 0x08
#define ADCCVL_ADCV4_MASK 0x10
#define ADCCVL_ADCV5_MASK 0x20
#define ADCCVL_ADCV6_MASK 0x40
#define ADCCVL_ADCV7_MASK 0x80
} Overlap_STR;
} ADCCVSTR;
extern volatile ADCCVSTR _ADCCV @0x00000014;
#define ADCCV _ADCCV.Word
/*** ADCCFG - Configuration Register; 0x00000016 ***/
typedef union {
byte Byte;
struct {
byte ADICLK0 :1; /* Input Clock Select Bit 0 */
byte ADICLK1 :1; /* Input Clock Select Bit 1 */
byte MODE0 :1; /* Conversion Mode Selection Bit 0 */
byte MODE1 :1; /* Conversion Mode Selection Bit 1 */
byte ADLSMP :1; /* Long Sample Time Configuration */
byte ADIV0 :1; /* Clock Divide Select Bit 0 */
byte ADIV1 :1; /* Clock Divide Select Bit 1 */
byte ADLPC :1; /* Low Power Configuration */
} Bits;
struct {
byte grpADICLK :2;
byte grpMODE :2;
byte :1;
byte grpADIV :2;
byte :1;
} MergedBits;
} ADCCFGSTR;
extern volatile ADCCFGSTR _ADCCFG @0x00000016;
#define ADCCFG _ADCCFG.Byte
#define ADCCFG_ADICLK0 _ADCCFG.Bits.ADICLK0
#define ADCCFG_ADICLK1 _ADCCFG.Bits.ADICLK1
#define ADCCFG_MODE0 _ADCCFG.Bits.MODE0
#define ADCCFG_MODE1 _ADCCFG.Bits.MODE1
#define ADCCFG_ADLSMP _ADCCFG.Bits.ADLSMP
#define ADCCFG_ADIV0 _ADCCFG.Bits.ADIV0
#define ADCCFG_ADIV1 _ADCCFG.Bits.ADIV1
#define ADCCFG_ADLPC _ADCCFG.Bits.ADLPC
#define ADCCFG_ADICLK _ADCCFG.MergedBits.grpADICLK
#define ADCCFG_MODE _ADCCFG.MergedBits.grpMODE
#define ADCCFG_ADIV _ADCCFG.MergedBits.grpADIV
#define ADCCFG_ADICLK0_MASK 0x01
#define ADCCFG_ADICLK1_MASK 0x02
#define ADCCFG_MODE0_MASK 0x04
#define ADCCFG_MODE1_MASK 0x08
#define ADCCFG_ADLSMP_MASK 0x10
#define ADCCFG_ADIV0_MASK 0x20
#define ADCCFG_ADIV1_MASK 0x40
#define ADCCFG_ADLPC_MASK 0x80
#define ADCCFG_ADICLK_MASK 0x03
#define ADCCFG_ADICLK_BITNUM 0x00
#define ADCCFG_MODE_MASK 0x0C
#define ADCCFG_MODE_BITNUM 0x02
#define ADCCFG_ADIV_MASK 0x60
#define ADCCFG_ADIV_BITNUM 0x05
/*** APCTL1 - Pin Control 1 Register; 0x00000017 ***/
typedef union {
byte Byte;
struct {
byte ADPC0 :1; /* ADC Pin Control 0 - ADPC0 is used to control the pin associated with channel AD0 */
byte ADPC1 :1; /* ADC Pin Control 1 - ADPC1 is used to control the pin associated with channel AD1 */
byte ADPC2 :1; /* ADC Pin Control 2 - ADPC2 is used to control the pin associated with channel AD2 */
byte ADPC3 :1; /* ADC Pin Control 3 - ADPC3 is used to control the pin associated with channel AD3 */
byte ADPC4 :1; /* ADC Pin Control 4 - ADPC4 is used to control the pin associated with channel AD4 */
byte ADPC5 :1; /* ADC Pin Control 5 - ADPC5 is used to control the pin associated with channel AD5 */
byte ADPC6 :1; /* ADC Pin Control 6 - ADPC6 is used to control the pin associated with channel AD6 */
byte ADPC7 :1; /* ADC Pin Control 7 - ADPC7 is used to control the pin associated with channel AD7 */
} Bits;
} APCTL1STR;
extern volatile APCTL1STR _APCTL1 @0x00000017;
#define APCTL1 _APCTL1.Byte
#define APCTL1_ADPC0 _APCTL1.Bits.ADPC0
#define APCTL1_ADPC1 _APCTL1.Bits.ADPC1
#define APCTL1_ADPC2 _APCTL1.Bits.ADPC2
#define APCTL1_ADPC3 _APCTL1.Bits.ADPC3
#define APCTL1_ADPC4 _APCTL1.Bits.ADPC4
#define APCTL1_ADPC5 _APCTL1.Bits.ADPC5
#define APCTL1_ADPC6 _APCTL1.Bits.ADPC6
#define APCTL1_ADPC7 _APCTL1.Bits.ADPC7
#define APCTL1_ADPC0_MASK 0x01
#define APCTL1_ADPC1_MASK 0x02
#define APCTL1_ADPC2_MASK 0x04
#define APCTL1_ADPC3_MASK 0x08
#define APCTL1_ADPC4_MASK 0x10
#define APCTL1_ADPC5_MASK 0x20
#define APCTL1_ADPC6_MASK 0x40
#define APCTL1_ADPC7_MASK 0x80
/*** SRS - System Reset Status Register; 0x00000018 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte LVD :1; /* Low Voltage Detect */
byte :1;
byte ILAD :1; /* Illegal Address */
byte ILOP :1; /* Illegal Opcode */
byte COP :1; /* Computer Operating Properly (COP) Watchdog */
byte PIN :1; /* External Reset Pin */
byte POR :1; /* Power-On Reset */
} Bits;
} SRSSTR;
extern volatile SRSSTR _SRS @0x00000018;
#define SRS _SRS.Byte
#define SRS_LVD _SRS.Bits.LVD
#define SRS_ILAD _SRS.Bits.ILAD
#define SRS_ILOP _SRS.Bits.ILOP
#define SRS_COP _SRS.Bits.COP
#define SRS_PIN _SRS.Bits.PIN
#define SRS_POR _SRS.Bits.POR
#define SRS_LVD_MASK 0x02
#define SRS_ILAD_MASK 0x08
#define SRS_ILOP_MASK 0x10
#define SRS_COP_MASK 0x20
#define SRS_PIN_MASK 0x40
#define SRS_POR_MASK 0x80
/*** SOPT - System Options Register; 0x00000019 ***/
typedef union {
byte Byte;
struct {
byte RSTPE :1; /* RESET Pin Enable */
byte BKGDPE :1; /* Background Debug Mode Pin Enable */
byte :1;
byte :1;
byte :1;
byte STOPE :1; /* Stop Mode Enable */
byte COPT :1; /* COP Watchdog Timeout */
byte COPE :1; /* COP Watchdog Enable */
} Bits;
} SOPTSTR;
extern volatile SOPTSTR _SOPT @0x00000019;
#define SOPT _SOPT.Byte
#define SOPT_RSTPE _SOPT.Bits.RSTPE
#define SOPT_BKGDPE _SOPT.Bits.BKGDPE
#define SOPT_STOPE _SOPT.Bits.STOPE
#define SOPT_COPT _SOPT.Bits.COPT
#define SOPT_COPE _SOPT.Bits.COPE
#define SOPT_RSTPE_MASK 0x01
#define SOPT_BKGDPE_MASK 0x02
#define SOPT_STOPE_MASK 0x20
#define SOPT_COPT_MASK 0x40
#define SOPT_COPE_MASK 0x80
/*** SIP1 - System Interrupt Pending Register 1; 0x0000001A ***/
typedef union {
byte Byte;
struct {
byte RTI :1; /* Real-Time Interrupt Pending */
byte LCD :1; /* LCD Interrupt Pending */
byte KBI :1; /* KBI Interrupt Pending */
byte ADC :1; /* ADC Interrupt Pending */
byte SCIE :1; /* SCI Error Interrupt Pending */
byte SCIR :1; /* SCI Receive Interrupt Pending */
byte SCIT :1; /* SCI Transmit Interrupt Pending */
byte LVD :1; /* LVD Interrupt Pending */
} Bits;
} SIP1STR;
extern volatile SIP1STR _SIP1 @0x0000001A;
#define SIP1 _SIP1.Byte
#define SIP1_RTI _SIP1.Bits.RTI
#define SIP1_LCD _SIP1.Bits.LCD
#define SIP1_KBI _SIP1.Bits.KBI
#define SIP1_ADC _SIP1.Bits.ADC
#define SIP1_SCIE _SIP1.Bits.SCIE
#define SIP1_SCIR _SIP1.Bits.SCIR
#define SIP1_SCIT _SIP1.Bits.SCIT
#define SIP1_LVD _SIP1.Bits.LVD
#define SIP1_RTI_MASK 0x01
#define SIP1_LCD_MASK 0x02
#define SIP1_KBI_MASK 0x04
#define SIP1_ADC_MASK 0x08
#define SIP1_SCIE_MASK 0x10
#define SIP1_SCIR_MASK 0x20
#define SIP1_SCIT_MASK 0x40
#define SIP1_LVD_MASK 0x80
/*** SIP2 - System Interrupt Pending Register 2; 0x0000001B ***/
typedef union {
byte Byte;
struct {
byte TPM1 :1; /* TPM1 Interrupt Pending */
byte TPM1CH0 :1; /* TPM1 Channel 0 Interrupt Pending */
byte TPM1CH1 :1; /* TPM1 Channel 1 Interrupt Pending */
byte :1;
byte TPM2 :1; /* TPM2 Interrupt Pending */
byte TPM2CH0 :1; /* TPM2 Channel 0 Interrupt Pending */
byte TPM2CH1 :1; /* TPM2 Channel 1 Interrupt Pending */
byte :1;
} Bits;
struct {
byte grpTPM_1 :1;
byte grpTPM1CH :2;
byte :1;
byte grpTPM_2 :1;
byte grpTPM2CH :2;
byte :1;
} MergedBits;
} SIP2STR;
extern volatile SIP2STR _SIP2 @0x0000001B;
#define SIP2 _SIP2.Byte
#define SIP2_TPM1 _SIP2.Bits.TPM1
#define SIP2_TPM1CH0 _SIP2.Bits.TPM1CH0
#define SIP2_TPM1CH1 _SIP2.Bits.TPM1CH1
#define SIP2_TPM2 _SIP2.Bits.TPM2
#define SIP2_TPM2CH0 _SIP2.Bits.TPM2CH0
#define SIP2_TPM2CH1 _SIP2.Bits.TPM2CH1
#define SIP2_TPM1CH _SIP2.MergedBits.grpTPM1CH
#define SIP2_TPM2CH _SIP2.MergedBits.grpTPM2CH
#define SIP2_TPM1_MASK 0x01
#define SIP2_TPM1CH0_MASK 0x02
#define SIP2_TPM1CH1_MASK 0x04
#define SIP2_TPM2_MASK 0x10
#define SIP2_TPM2CH0_MASK 0x20
#define SIP2_TPM2CH1_MASK 0x40
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