scc.c.svn-base

PowerPC850系列的產品開機程式uboot是linuxOS BASED的程式碼

	pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]);	/* Set TXBD tbl start at Dual Port */

	/*
	 * Setup Receiver Buffer Descriptors (13.14.24.18)
	 * Settings:
	 *     Empty, Wrap
	 */

	for (i = 0; i < PKTBUFSRX; i++) {
		rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
		rtx->rxbd[i].cbd_datlen = 0;	/* Reset */
		rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
	}

	rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;

	/*
	 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
	 * Settings:
	 *    Add PADs to Short FRAMES, Wrap, Last, Tx CRC
	 */

	for (i = 0; i < TX_BUF_CNT; i++) {
		rtx->txbd[i].cbd_sc =
			(BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
		rtx->txbd[i].cbd_datlen = 0;	/* Reset */
		rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
	}

	rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;

	/*
	 * Enter Command:  Initialize Rx Params for SCC
	 */

	do {			/* Spin until ready to issue command    */
		__asm__ ("eieio");
	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	/* Issue command */
	immr->im_cpm.cp_cpcr =
		((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
	do {			/* Spin until command processed         */
		__asm__ ("eieio");
	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);

	/*
	 * Ethernet Specific Parameter RAM
	 *     see table 13-16, pg. 660,
	 *     pg. 681 (example with suggested settings)
	 */

	pram_ptr->sen_cpres = ~(0x0);	/* Preset CRC */
	pram_ptr->sen_cmask = 0xdebb20e3;	/* Constant Mask for CRC */
	pram_ptr->sen_crcec = 0x0;	/* Error Counter CRC (unused) */
	pram_ptr->sen_alec = 0x0;	/* Alignment Error Counter (unused) */
	pram_ptr->sen_disfc = 0x0;	/* Discard Frame Counter (unused) */
	pram_ptr->sen_pads = 0x8888;	/* Short Frame PAD Characters */

	pram_ptr->sen_retlim = 15;	/* Retry Limit Threshold */
	pram_ptr->sen_maxflr = 1518;	/* MAX Frame Length Register */
	pram_ptr->sen_minflr = 64;	/* MIN Frame Length Register */

	pram_ptr->sen_maxd1 = DBUF_LENGTH;	/* MAX DMA1 Length Register */
	pram_ptr->sen_maxd2 = DBUF_LENGTH;	/* MAX DMA2 Length Register */

	pram_ptr->sen_gaddr1 = 0x0;	/* Group Address Filter 1 (unused) */
	pram_ptr->sen_gaddr2 = 0x0;	/* Group Address Filter 2 (unused) */
	pram_ptr->sen_gaddr3 = 0x0;	/* Group Address Filter 3 (unused) */
	pram_ptr->sen_gaddr4 = 0x0;	/* Group Address Filter 4 (unused) */

#define ea eth_get_dev()->enetaddr
	pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
	pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
	pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
#undef ea

	pram_ptr->sen_pper = 0x0;	/* Persistence (unused) */
	pram_ptr->sen_iaddr1 = 0x0;	/* Individual Address Filter 1 (unused) */
	pram_ptr->sen_iaddr2 = 0x0;	/* Individual Address Filter 2 (unused) */
	pram_ptr->sen_iaddr3 = 0x0;	/* Individual Address Filter 3 (unused) */
	pram_ptr->sen_iaddr4 = 0x0;	/* Individual Address Filter 4 (unused) */
	pram_ptr->sen_taddrh = 0x0;	/* Tmp Address (MSB) (unused) */
	pram_ptr->sen_taddrm = 0x0;	/* Tmp Address (unused) */
	pram_ptr->sen_taddrl = 0x0;	/* Tmp Address (LSB) (unused) */

	/*
	 * Enter Command:  Initialize Tx Params for SCC
	 */

	do {			/* Spin until ready to issue command    */
		__asm__ ("eieio");
	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	/* Issue command */
	immr->im_cpm.cp_cpcr =
		((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
	do {			/* Spin until command processed         */
		__asm__ ("eieio");
	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);

	/*
	 * Mask all Events in SCCM - we use polling mode
	 */
	immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;

	/*
	 * Clear Events in SCCE -- Clear bits by writing 1's
	 */

	immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);


	/*
	 * Initialize GSMR High 32-Bits
	 * Settings:  Normal Mode
	 */

	immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;

	/*
	 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
	 * Settings:
	 *     TCI = Invert
	 *     TPL =  48 bits
	 *     TPP = Repeating 10's
	 *     MODE = Ethernet
	 */

	immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI |
						   SCC_GSMRL_TPL_48 |
						   SCC_GSMRL_TPP_10 |
						   SCC_GSMRL_MODE_ENET);

	/*
	 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
	 */

	immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;

	/*
	 * Initialize the PSMR
	 * Settings:
	 *  CRC = 32-Bit CCITT
	 *  NIB = Begin searching for SFD 22 bits after RENA
	 *  FDE = Full Duplex Enable
	 *  LPB = Loopback Enable (Needed when FDE is set)
	 *  BRO = Reject broadcast packets
	 *  PROMISCOUS = Catch all packets regardless of dest. MAC adress
	 */
	immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
		SCC_PSMR_NIB22 |
#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
		SCC_PSMR_FDE | SCC_PSMR_LPB |
#endif
#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
		SCC_PSMR_BRO |
#endif
#if defined(CONFIG_SCC_ENET_PROMISCOUS)
		SCC_PSMR_PRO |
#endif
		0;

	/*
	 * Configure Ethernet TENA Signal
	 */

#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
	immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
	immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
	immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
	immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
#else
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
#endif

#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
	/*
	 * Port C is used to control the PHY,MC68160.
	 */
	immr->im_ioport.iop_pcdir |=
		(PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);

	immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
	immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
	*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif /* MPC860ADS */

#if defined(CONFIG_AMX860)
	/*
	 * Port B is used to control the PHY,MC68160.
	 */
	immr->im_cpm.cp_pbdir |=
		(PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);

	immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
	immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);

	immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
	immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
#endif /* AMX860 */

#ifdef CONFIG_RPXCLASSIC
	*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
	*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
#endif

#ifdef CONFIG_RPXLITE
	*((uchar *) BCSR0) |= BCSR0_ETHEN;
#endif

#if defined(CONFIG_QS860T)
	/*
	 * PB27=FDE-, set output low for full duplex
	 * PB26=Link Test Enable, normally high output
	 */
	immr->im_cpm.cp_pbdir |= 0x00000030;
	immr->im_cpm.cp_pbdat |= 0x00000020;
	immr->im_cpm.cp_pbdat &= ~0x00000010;
#endif /* QS860T */

#ifdef CONFIG_MBX
	board_ether_init ();
#endif

#if defined(CONFIG_NETVIA)
#if defined(PA_ENET_PDN)
	immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
	immr->im_ioport.iop_padir |= PA_ENET_PDN;
	immr->im_ioport.iop_padat |= PA_ENET_PDN;
#elif defined(PB_ENET_PDN)
	immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
	immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
	immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
#elif defined(PC_ENET_PDN)
	immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
	immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
	immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
#elif defined(PD_ENET_PDN)
	immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
	immr->im_ioport.iop_pddir |= PD_ENET_PDN;
	immr->im_ioport.iop_pddat |= PD_ENET_PDN;
#endif
#endif

	/*
	 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
	 */

	immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
		(SCC_GSMRL_ENR | SCC_GSMRL_ENT);

	/*
	 * Work around transmit problem with first eth packet
	 */
#if defined (CONFIG_FADS)
	udelay (10000);		/* wait 10 ms */
#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
	udelay (100000);	/* wait 100 ms */
#endif

	return 1;
}


static void scc_halt (struct eth_device *dev)
{
	volatile immap_t *immr = (immap_t *) CFG_IMMR;

	immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &=
		~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);

	immr->im_ioport.iop_pcso  &=  ~(PC_ENET_CLSN | PC_ENET_RENA);
}

#if 0
void restart (void)
{
	volatile immap_t *immr = (immap_t *) CFG_IMMR;

	immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
		(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
#endif
#endif	/* CFG_CMD_NET, SCC_ENET */