scc.c.svn-base

PowerPC850系列的產品開機程式uboot是linuxOS BASED的程式碼

/*
 * File:  scc.c
 * Description:
 * 	Basic ET HW initialization and packet RX/TX routines
 *
 * NOTE  <<<IMPORTANT:  PLEASE READ>>>:
 *     Do not cache Rx/Tx buffers!
 */

/*
 * MPC823 <-> MC68160 Connections:
 *
 * Setup MPC823 to work with MC68160 Enhanced Ethernet
 * Serial Tranceiver as follows:
 *
 * MPC823 Signal                MC68160  Comments
 * ------ ------                -------  --------
 * PA-12 ETHTX    -------->   TX       Eth. Port Transmit Data
 * PB-18 E_TENA   -------->   TENA     Eth. Transmit Port Enable
 * PA-5 ETHTCK    <--------   TCLK     Eth. Port Transmit Clock
 * PA-13 ETHRX    <--------   RX       Eth. Port Receive Data
 * PC-8 E_RENA    <--------   RENA     Eth. Receive Enable
 * PA-6 ETHRCK    <--------   RCLK     Eth. Port Receive Clock
 * PC-9 E_CLSN    <--------   CLSN     Eth. Port Collision Indication
 *
 * FADS Board Signal              MC68160  Comments
 * -----------------              -------  --------
 * (BCSR1) ETHEN*     -------->  CS2      Eth. Port Enable
 * (BSCR4) TPSQEL*    -------->  TPSQEL   Twisted Pair Signal Quality Error Test Enable
 * (BCSR4) TPFLDL*    -------->  TPFLDL   Twisted Pair Full-Duplex
 * (BCSR4) ETHLOOP    -------->  LOOP     Eth. Port Diagnostic Loop-Back
 *
 */

#include <common.h>
#include <malloc.h>
#include <commproc.h>
#include <net.h>
#include <command.h>

#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET)

/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH  1520

#define TX_BUF_CNT 2

#define TOUT_LOOP 10000	/* 10 ms to have a packet sent */

static char txbuf[DBUF_LENGTH];

static uint rxIdx;	/* index of the current RX buffer */
static uint txIdx;	/* index of the current TX buffer */

/*
  * SCC Ethernet Tx and Rx buffer descriptors allocated at the
  *  immr->udata_bd address on Dual-Port RAM
  * Provide for Double Buffering
  */

typedef volatile struct CommonBufferDescriptor {
    cbd_t rxbd[PKTBUFSRX];	/* Rx BD */
    cbd_t txbd[TX_BUF_CNT];	/* Tx BD */
} RTXBD;

static RTXBD *rtx;

static int scc_send(struct eth_device* dev, volatile void *packet, int length);
static int scc_recv(struct eth_device* dev);
static int scc_init (struct eth_device* dev, bd_t * bd);
static void scc_halt(struct eth_device* dev);

int scc_initialize(bd_t *bis)
{
	struct eth_device* dev;

	dev = (struct eth_device*) malloc(sizeof *dev);
	memset(dev, 0, sizeof *dev);

	sprintf(dev->name, "SCC ETHERNET");
	dev->iobase = 0;
	dev->priv   = 0;
	dev->init   = scc_init;
	dev->halt   = scc_halt;
	dev->send   = scc_send;
	dev->recv   = scc_recv;

	eth_register(dev);

	return 1;
}

static int scc_send(struct eth_device* dev, volatile void *packet, int length)
{
	int i, j=0;
#if 0
	volatile char *in, *out;
#endif

	/* section 16.9.23.3
	 * Wait for ready
	 */
#if 0
	while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY);
	out = (char *)(rtx->txbd[txIdx].cbd_bufaddr);
	in = packet;
	for(i = 0; i < length; i++) {
		*out++ = *in++;
	}
	rtx->txbd[txIdx].cbd_datlen = length;
	rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST);
	while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++;

#ifdef ET_DEBUG
	printf("cycles: %d    status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
#endif
	i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;

	/* wrap around buffer index when necessary */
	if (txIdx >= TX_BUF_CNT) txIdx = 0;
#endif

	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
		udelay (1);	/* will also trigger Wd if needed */
		j++;
	}
	if (j>=TOUT_LOOP) printf("TX not ready\n");
	rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
	rtx->txbd[txIdx].cbd_datlen = length;
	rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP);
	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
		udelay (1);	/* will also trigger Wd if needed */
		j++;
	}
	if (j>=TOUT_LOOP) printf("TX timeout\n");
#ifdef ET_DEBUG
	printf("cycles: %d    status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
#endif
	i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
	return i;
}

static int scc_recv (struct eth_device *dev)
{
	int length;

	for (;;) {
		/* section 16.9.23.2 */
		if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
			length = -1;
			break;	/* nothing received - leave for() loop */
		}

		length = rtx->rxbd[rxIdx].cbd_datlen;

		if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
#ifdef ET_DEBUG
			printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
#endif
		} else {
			/* Pass the packet up to the protocol layers. */
			NetReceive (NetRxPackets[rxIdx], length - 4);
		}


		/* Give the buffer back to the SCC. */
		rtx->rxbd[rxIdx].cbd_datlen = 0;

		/* wrap around buffer index when necessary */
		if ((rxIdx + 1) >= PKTBUFSRX) {
			rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
				(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
			rxIdx = 0;
		} else {
			rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
			rxIdx++;
		}
	}
	return length;
}

/**************************************************************
  *
  * SCC Ethernet Initialization Routine
  *
  *************************************************************/

static int scc_init (struct eth_device *dev, bd_t * bis)
{

	int i;
	scc_enet_t *pram_ptr;

	volatile immap_t *immr = (immap_t *) CFG_IMMR;

#if defined(CONFIG_LWMON)
	reset_phy();
#endif

#ifdef CONFIG_FADS
#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
	/* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
	*((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
	*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
	*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#else
	*((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
	*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
	*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif
#endif

	pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);

	rxIdx = 0;
	txIdx = 0;

#ifdef CFG_ALLOC_DPRAM
	rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
			 dpram_alloc_align (sizeof (RTXBD), 8));
#else
	rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
#endif /* 0 */

#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
	/* Configure port A pins for Txd and Rxd.
	 */
	immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
	immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
	immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
	/* Configure port B pins for Txd and Rxd.
	 */
	immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
	immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
	immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
#else
#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
#endif

#if defined(PC_ENET_LBK)
	/* Configure port C pins to disable External Loopback
	 */
	immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
	immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
	immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
	immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK;	/* Disable Loopback */
#endif /* PC_ENET_LBK */

	/* Configure port C pins to enable CLSN and RENA.
	 */
	immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
	immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
	immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);

	/* Configure port A for TCLK and RCLK.
	 */
	immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
	immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);

	/*
	 * Configure Serial Interface clock routing -- see section 16.7.5.3
	 * First, clear all SCC bits to zero, then set the ones we want.
	 */

	immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
	immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;


	/*
	 * Initialize SDCR -- see section 16.9.23.7
	 * SDMA configuration register
	 */
	immr->im_siu_conf.sc_sdcr = 0x01;


	/*
	 * Setup SCC Ethernet Parameter RAM
	 */

	pram_ptr->sen_genscc.scc_rfcr = 0x18;	/* Normal Operation and Mot byte ordering */
	pram_ptr->sen_genscc.scc_tfcr = 0x18;	/* Mot byte ordering, Normal access */

	pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH;	/* max. ET package len 1520 */

	pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]);	/* Set RXBD tbl start at Dual Port */