📄 start.s.svn-base
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addis r4, r0, CFG_DBAT2L@h ori r4, r4, CFG_DBAT2L@l addis r3, r0, CFG_DBAT2U@h ori r3, r3, CFG_DBAT2U@l mtspr DBAT2L, r4 mtspr DBAT2U, r3 isync /* IBAT 3 */ addis r4, r0, CFG_IBAT3L@h ori r4, r4, CFG_IBAT3L@l addis r3, r0, CFG_IBAT3U@h ori r3, r3, CFG_IBAT3U@l mtspr IBAT3L, r4 mtspr IBAT3U, r3 isync /* DBAT 3 */ addis r4, r0, CFG_DBAT3L@h ori r4, r4, CFG_DBAT3L@l addis r3, r0, CFG_DBAT3U@h ori r3, r3, CFG_DBAT3U@l mtspr DBAT3L, r4 mtspr DBAT3U, r3 isync#if (CFG_HID2 & HID2_HBE) /* IBAT 4 */ addis r4, r0, CFG_IBAT4L@h ori r4, r4, CFG_IBAT4L@l addis r3, r0, CFG_IBAT4U@h ori r3, r3, CFG_IBAT4U@l mtspr IBAT4L, r4 mtspr IBAT4U, r3 isync /* DBAT 4 */ addis r4, r0, CFG_DBAT4L@h ori r4, r4, CFG_DBAT4L@l addis r3, r0, CFG_DBAT4U@h ori r3, r3, CFG_DBAT4U@l mtspr DBAT4L, r4 mtspr DBAT4U, r3 isync /* IBAT 5 */ addis r4, r0, CFG_IBAT5L@h ori r4, r4, CFG_IBAT5L@l addis r3, r0, CFG_IBAT5U@h ori r3, r3, CFG_IBAT5U@l mtspr IBAT5L, r4 mtspr IBAT5U, r3 isync /* DBAT 5 */ addis r4, r0, CFG_DBAT5L@h ori r4, r4, CFG_DBAT5L@l addis r3, r0, CFG_DBAT5U@h ori r3, r3, CFG_DBAT5U@l mtspr DBAT5L, r4 mtspr DBAT5U, r3 isync /* IBAT 6 */ addis r4, r0, CFG_IBAT6L@h ori r4, r4, CFG_IBAT6L@l addis r3, r0, CFG_IBAT6U@h ori r3, r3, CFG_IBAT6U@l mtspr IBAT6L, r4 mtspr IBAT6U, r3 isync /* DBAT 6 */ addis r4, r0, CFG_DBAT6L@h ori r4, r4, CFG_DBAT6L@l addis r3, r0, CFG_DBAT6U@h ori r3, r3, CFG_DBAT6U@l mtspr DBAT6L, r4 mtspr DBAT6U, r3 isync /* IBAT 7 */ addis r4, r0, CFG_IBAT7L@h ori r4, r4, CFG_IBAT7L@l addis r3, r0, CFG_IBAT7U@h ori r3, r3, CFG_IBAT7U@l mtspr IBAT7L, r4 mtspr IBAT7U, r3 isync /* DBAT 7 */ addis r4, r0, CFG_DBAT7L@h ori r4, r4, CFG_DBAT7L@l addis r3, r0, CFG_DBAT7U@h ori r3, r3, CFG_DBAT7U@l mtspr DBAT7L, r4 mtspr DBAT7U, r3 isync#endif /* Invalidate TLBs. * -> for (val = 0; val < 0x20000; val+=0x1000) * -> tlbie(val); */ lis r3, 0 lis r5, 21: tlbie r3 addi r3, r3, 0x1000 cmp 0, 0, r3, r5 blt 1b blr .globl enable_addr_transenable_addr_trans: /* enable address translation */ mfmsr r5 ori r5, r5, (MSR_IR | MSR_DR) mtmsr r5 isync blr .globl disable_addr_transdisable_addr_trans: /* disable address translation */ mflr r4 mfmsr r3 andi. r0, r3, (MSR_IR | MSR_DR) beqlr andc r3, r3, r0 mtspr SRR0, r4 mtspr SRR1, r3 rfi/* Cache functions. * * Note: requires that all cache bits in * HID0 are in the low half word. */ .globl icache_enableicache_enable: mfspr r3, HID0 ori r3, r3, HID0_ICE lis r4, 0 ori r4, r4, HID0_ILOCK andc r3, r3, r4 ori r4, r3, HID0_ICFI isync mtspr HID0, r4 /* sets enable and invalidate, clears lock */ isync mtspr HID0, r3 /* clears invalidate */ blr .globl icache_disableicache_disable: mfspr r3, HID0 lis r4, 0 ori r4, r4, HID0_ICE|HID0_ILOCK andc r3, r3, r4 ori r4, r3, HID0_ICFI isync mtspr HID0, r4 /* sets invalidate, clears enable and lock*/ isync mtspr HID0, r3 /* clears invalidate */ blr .globl icache_statusicache_status: mfspr r3, HID0 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 blr .globl dcache_enabledcache_enable: mfspr r3, HID0 li r5, HID0_DCFI|HID0_DLOCK andc r3, r3, r5 mtspr HID0, r3 /* no invalidate, unlock */ ori r3, r3, HID0_DCE ori r5, r3, HID0_DCFI mtspr HID0, r5 /* enable + invalidate */ mtspr HID0, r3 /* enable */ sync blr .globl dcache_disabledcache_disable: mfspr r3, HID0 lis r4, 0 ori r4, r4, HID0_DCE|HID0_DLOCK andc r3, r3, r4 ori r4, r3, HID0_DCI sync mtspr HID0, r4 /* sets invalidate, clears enable and lock */ sync mtspr HID0, r3 /* clears invalidate */ blr .globl dcache_statusdcache_status: mfspr r3, HID0 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 blr .globl get_pvrget_pvr: mfspr r3, PVR blr/*------------------------------------------------------------------------------- *//* Function: ppcDcbf *//* Description: Data Cache block flush *//* Input: r3 = effective address *//* Output: none. *//*------------------------------------------------------------------------------- */ .globl ppcDcbfppcDcbf: dcbf r0,r3 blr/*------------------------------------------------------------------------------- *//* Function: ppcDcbi *//* Description: Data Cache block Invalidate *//* Input: r3 = effective address *//* Output: none. *//*------------------------------------------------------------------------------- */ .globl ppcDcbippcDcbi: dcbi r0,r3 blr/*-------------------------------------------------------------------------- * Function: ppcDcbz * Description: Data Cache block zero. * Input: r3 = effective address * Output: none. *-------------------------------------------------------------------------- */ .globl ppcDcbzppcDcbz: dcbz r0,r3 blr/*-------------------------------------------------------------------*//* * void relocate_code (addr_sp, gd, addr_moni) * * This "function" does not return, instead it continues in RAM * after relocating the monitor code. * * r3 = dest * r4 = src * r5 = length in bytes * r6 = cachelinesize */ .globl relocate_coderelocate_code: mr r1, r3 /* Set new stack pointer */ mr r9, r4 /* Save copy of Global Data pointer */ mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ lis r4, CFG_MONITOR_BASE@h /* Source Address */ ori r4, r4, CFG_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) * + Destination Address * * Offset: */ sub r15, r10, r4 /* First our own GOT */ add r14, r14, r15 /* then the one used by the C code */ add r30, r30, r15 /* * Now relocate code */ cmplw cr1,r3,r4 addi r0,r5,3 srwi. r0,r0,2 beq cr1,4f /* In place copy is not necessary */ beq 7f /* Protect against 0 count */ mtctr r0 bge cr1,2f la r8,-4(r4) la r7,-4(r3) /* copy */1: lwzu r0,4(r8) stwu r0,4(r7) bdnz 1b addi r0,r5,3 srwi. r0,r0,2 mtctr r0 la r8,-4(r4) la r7,-4(r3) /* and compare */20: lwzu r20,4(r8) lwzu r21,4(r7) xor. r22, r20, r21 bne 30f bdnz 20b b 4f /* compare failed */30: li r3, 0 blr2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ add r8,r4,r0 add r7,r3,r03: lwzu r0,-4(r8) stwu r0,-4(r7) bdnz 3b/* * Now flush the cache: note that we must start from a cache aligned * address. Otherwise we might miss one cache line. */4: cmpwi r6,0 add r5,r3,r5 beq 7f /* Always flush prefetch queue in any case */ subi r0,r6,1 andc r3,r3,r0 mr r4,r35: dcbst 0,r4 add r4,r4,r6 cmplw r4,r5 blt 5b sync /* Wait for all dcbst to complete on bus */ mr r4,r36: icbi 0,r4 add r4,r4,r6 cmplw r4,r5 blt 6b7: sync /* Wait for all icbi to complete on bus */ isync/* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET mtlr r0 blrin_ram: /* * Relocation Function, r14 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. */ li r0,__got2_entries@sectoff@l la r3,GOT(_GOT2_TABLE_) lwz r11,GOT(_GOT2_TABLE_) mtctr r0 sub r11,r3,r11 addi r3,r3,-41: lwzu r0,4(r3) add r0,r0,r11 stw r0,0(r3) bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */2: li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 addi r3,r3,-4 beq 4f3: lwzu r4,4(r3) lwzux r0,r4,r11 add r0,r0,r11 stw r10,0(r3) stw r0,0(r4) bdnz 3b4:clear_bss: /* * Now clear BSS segment */ lwz r3,GOT(__bss_start)#if defined(CONFIG_HYMOD) /* * For HYMOD - the environment is the very last item in flash. * The real .bss stops just before environment starts, so only * clear up to that point. * * taken from mods for FADS board */ lwz r4,GOT(environment)#else lwz r4,GOT(_end)#endif cmplw 0, r3, r4 beq 6f li r0, 05: stw r0, 0(r3) addi r3, r3, 4 cmplw 0, r3, r4 bne 5b6: mr r3, r9 /* Global Data pointer */ mr r4, r10 /* Destination Address */ bl board_init_r /* * Copy exception vector code to low memory * * r3: dest_addr * r7: source address, r8: end address, r9: target address */ .globl trap_inittrap_init: lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) li r9, 0x100 /* reset vector always at 0x100 */ cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ mflr r4 /* save link register */1: lwz r0, 0(r7) stw r0, 0(r9) addi r7, r7, 4 addi r9, r9, 4 cmplw 0, r7, r8 bne 1b /* * relocate `hdlr' and `int_return' entries */ li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET li r8, Alignment - _start + EXC_OFF_SYS_RESET2: bl trap_reloc addi r7, r7, 0x100 /* next exception vector */ cmplw 0, r7, r8 blt 2b li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET bl trap_reloc li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET bl trap_reloc li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET li r8, SystemCall - _start + EXC_OFF_SYS_RESET3: bl trap_reloc addi r7, r7, 0x100 /* next exception vector */ cmplw 0, r7, r8 blt 3b li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET4: bl trap_reloc addi r7, r7, 0x100 /* next exception vector */ cmplw 0, r7, r8 blt 4b mfmsr r3 /* now that the vectors have */ lis r7, MSR_IP@h /* relocated into low memory */ ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ andc r3, r3, r7 /* (if it was on) */ SYNC /* Some chip revs need this... */ mtmsr r3 SYNC mtlr r4 /* restore link register */ blr /* * Function: relocate entries for one exception vector */trap_reloc: lwz r0, 0(r7) /* hdlr ... */ add r0, r0, r3 /* ... += dest_addr */ stw r0, 0(r7) lwz r0, 4(r7) /* int_return ... */ add r0, r0, r3 /* ... += dest_addr */ stw r0, 4(r7) blr#ifdef CFG_INIT_RAM_LOCKlock_ram_in_cache: /* Allocate Initial RAM in data cache. */ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l li r2, ((CFG_INIT_RAM_END & ~31) + \ (CFG_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r21: dcbz r0, r3 addi r3, r3, 32 bdnz 1b /* Lock the data cache */ mfspr r0, HID0 ori r0, r0, 0x1000 sync mtspr HID0, r0 sync blr.globl unlock_ram_in_cacheunlock_ram_in_cache: /* invalidate the INIT_RAM section */ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l li r2,512 mtctr r21: icbi r0, r3 dcbi r0, r3 addi r3, r3, 32 bdnz 1b sync /* Wait for all icbi to complete on bus */ isync /* Unlock the data cache and invalidate it */ mfspr r3, HID0 li r5, HID0_DLOCK|HID0_DCFI andc r3, r3, r5 /* no invalidate, unlock */ ori r5, r3, HID0_DCFI /* invalidate, unlock */ mtspr HID0, r5 /* invalidate, unlock */ mtspr HID0, r3 /* no invalidate, unlock */ sync blr#endifmap_flash_by_law1: /* When booting from ROM (Flash or EPROM), clear the */ /* Address Mask in OR0 so ROM appears everywhere */ /*----------------------------------------------------*/ lis r3, (CFG_IMMRBAR)@h /* r3 <= CFG_IMMRBAR */ lwz r4, OR0@l(r3) li r5, 0x7fff /* r5 <= 0x00007FFFF */ and r4, r4, r5 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is * 0xFF800. From the hard resetting to here, the processor fetched and * executed the instructions one by one. There is not absolutely * jumping happened. Laterly, the u-boot code has to do an absolutely * jumping to tell the CPU instruction fetching component what the * u-boot TEXT base address is. Because the TEXT base resides in the * boot ROM memory space, to garantee the code can run smoothly after * that jumping, we must map in the entire boot ROM by Local Access * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting * address for boot ROM, such as 0xFE000000. In this case, the default * LBIU Local Access Widow 0 will not cover this memory space. So, we * need another window to map in it. */ lis r4, (CFG_FLASH_BASE)@h ori r4, r4, (CFG_FLASH_BASE)@l stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */ lis r4, (0x80000016)@h ori r4, r4, (0x80000016)@l stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ blr /* Though all the LBIU Local Access Windows and LBC Banks will be * initialized in the C code, we'd better configure boot ROM's * window 0 and bank 0 correctly at here. */remap_flash_by_law0: /* Initialize the BR0 with the boot ROM starting address. */ lwz r4, BR0(r3) li r5, 0x7FFF and r4, r4, r5 lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l or r5, r5, r4 stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ lwz r4, OR0(r3) lis r5, 0xFF80 /* 8M */ or r4, r4, r5 stw r4, OR0(r3) /* OR0 <= OR0 | 0xFF800000 */ lis r4, (CFG_FLASH_BASE)@h ori r4, r4, (CFG_FLASH_BASE)@l stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */ lis r4, (0x80000016)@h ori r4, r4, (0x80000016)@l stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= 8MB Flash Size */ xor r4, r4, r4 stw r4, LBLAWBAR1(r3) stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ blr⌨️ 快捷键说明
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