core_i2c.h

6440linuxDriver的源代码

/*
========================================================================
64xx chip registers BAR 2
========================================================================
*/

#define	MV_PCI_BAR2                       2

#define I2C_SOFTWARE_CONTROL              0x1c
#define I2C_HARDWARE_CONTROL              0x20
#define I2C_STATUS_DATA                   0x24

		/* I2C_SOFTWARE_CONTROL bits */
typedef struct _REG_I2C_SOFTWARE_CONTROL
{
	MV_U32	DATA_PORT:8;
	MV_U32	ADRS_PORT:3;
	MV_U32	Reserved1:1;
	MV_U32	WRITE_EN:1;
	MV_U32	READ_EN:1;
	MV_U32	Reserved2:18;
} REG_I2C_SOFTWARE_CONTROL, *PREG_I2C_SOFTWARE_CONTROL;

/* ADRS_PORT values,  MI2C register address */
#define MI2C_SLAVE_ADDRESS		0x0
#define MI2C_X_SLAVE_ADDRESS	0x4
#define MI2C_DATA				0x1
#define MI2C_CONTROL			0x2
#define MI2C_STATUS				0x3 /* READ */
#define MI2C_CLOCK_CONTROL		0x3 /* WRITE */
#define MI2C_SOFT_RESET			0x7

		/* MI2C_SLAVE_ADDRESS bits */
typedef struct _REG_MI2C_SLAVE_ADDRESS
{
	MV_U8	GCE:1; /* general call address enable */
	MV_U8	SLA:7; /* Slave address 0-6 */
} REG_MI2C_SLAVE_ADDRESS, *PREG_MI2C_SLAVE_ADDRESS;

		/* MI2C_CONTROL bits */
typedef struct _REG_MI2C_CONTROL
{
	MV_U8	Reserved:2;
	MV_U8	AAK:1; /* Assert AcKnowledge */
	MV_U8	IFLG:1; /* Interrupt FLaG */
	MV_U8	STP:1; /* Master Stop */
	MV_U8	STA:1; /* Master Start */
	MV_U8	ENAB:1; /* Bus Enable */
	MV_U8	IEN:1; /* Interrupt Enable */
} REG_MI2C_CONTROL, *PREG_MI2C_CONTROL;

		/* MI2C_STATUS bits */
#define MI2C_STATUS_BUS_ERROR				0x00
#define MI2C_STATUS_START_TX				0x08
#define MI2C_STATUS_REP_START_TX			0x10
#define MI2C_STATUS_ADDR_W_TX_ACK			0x18
#define MI2C_STATUS_ADDR_W_TX_NAK			0x20
#define MI2C_STATUS_MDATA_TX_ACK			0x28
#define MI2C_STATUS_MDATA_TX_NAK			0x30
#define MI2C_STATUS_ARBLST_ADDR_DATA		0x38
#define MI2C_STATUS_ADDR_R_TX_ACK			0x40
#define MI2C_STATUS_ADDR_R_TX_NAK			0x48
#define MI2C_STATUS_MDATA_RX_ACK			0x50
#define MI2C_STATUS_MDATA_RX_NAK			0x58
#define MI2C_STATUS_SADDR_W_RX_ACK			0x60
#define MI2C_STATUS_ARBLST_SADDR_W_RX_ACK	0x68
#define MI2C_STATUS_GC_ADDR_RX_ACK			0x70
#define MI2C_STATUS_ARBLST_GC_RX_ACK		0x78
#define MI2C_STATUS_SADDR_DATA_RX_ACK		0x80
#define MI2C_STATUS_SADDR_DATA_RX_NAK		0x88
#define MI2C_STATUS_GC_DATA_RX_ACK			0x90
#define MI2C_STATUS_GC_DATA_RX_NAK			0x98
#define MI2C_STATUS_STOP_RX					0xA0
#define MI2C_STATUS_SADDR_R_RX_ACK			0xA8
#define MI2C_STATUS_ARBLST_SADDR_R_RX_ACK	0xB0
#define MI2C_STATUS_SDATA_TX_ACK			0xB8
#define MI2C_STATUS_SDATA_TX_NAK			0xC0
#define MI2C_STATUS_LAST_SDATA_TX_ACK		0xC8
#define MI2C_STATUS_ADDR2_W_TX_ACK			0xD0
#define MI2C_STATUS_ADDR2_W_TX_NAK			0xD8
#define MI2C_STATUS_ADDR2_R_TX_ACK			0xE0
#define MI2C_STATUS_ADDR2_R_TX_NAK			0xE8
#define MI2C_STATUS_NONE					0xF8

/* I2C_State in Core_Driver_Extension*/
enum 
{
	I2C_STATE_IDLE=0,
	I2C_STATE_CMD,
	I2C_STATE_RESPONSE,
	I2C_STATE_ERROR
};

		/* I2C_HARDWARE_CONTROL bits */
typedef struct _REG_I2C_HARDWARE_CONTROL
{
	MV_U32	SLV_ADRS:8;
	MV_U32	BUS_PTL:8;
	MV_U32	CMD_CODE:8;
	MV_U32	BUS_PTL_START:1;
	MV_U32	Reserved:6;
	MV_U32	INT:1;
} REG_I2C_HARDWARE_CONTROL, *PREG_I2C_HARDWARE_CONTROL;

/* BUS_PTL value*/
#define BUS_PTL_WRITE_QUICK	0 /* Write quick. */
#define BUS_PTL_READ_QUICK	0x01 /* Read quick. */
#define BUS_PTL_SEND_BYTE	0x02 /* Send byte. */
#define BUS_PTL_RCV_BYTE	0x03 /* Receive byte. */
#define BUS_PTL_WRITE_BYTE	0x04 /* Write byte. */
#define BUS_PTL_READ_BYTE	0x05 /* Read byte. */
#define BUS_PTL_WRITE_WORD	0x06 /* Write word. */
#define BUS_PTL_READ_WORD	0x07 /* Read word. */
#define BUS_PTL_RCV_WORD	0x0F /* Receive word. */

		/* I2C_STATUS_DATA bits */
typedef struct _REG_I2C_STATUS_DATA
{
	MV_U32	DATA_LO:8;
	MV_U32	DATA_HI:8;
	MV_U32	Reserved:8;
	MV_U32	INT_ST:8; /* for INT_ST value, see MI2C_STATUS */
} REG_I2C_STATUS_DATA, *PREG_I2C_STATUS_DATA;

/* 150MHz/10 */
#define I2C_SYS_CLOCK           150000000/10

/* I2C link rate definitions */
#define  I2C_LINK_RATE        100*1000          /* 100 kbps   */
//#define  I2C_LINK_RATE        400*1000          /* 400 kbps   */

/*
 Definition for SES commands over I2C (to SEP)

Key components:
[SEP address] - [R/W direction] - [Command Type] - [Checksum] - [SEMB address] - [Seq number] -
[SEP/SES commands] - [Data...
*/

/* [SEP address] */
#define I2C_SEP_ADDR0       0xC0 /* i2c address for SEP 0           */
#define I2C_SEP_ADDR1       0xC2 /* i2c address for SEP 1           */

/* [SEMB address] */
#define I2C_SEMB_ADDR        0xD0 /* i2c address for SEMB           */


/* SEP ATA command code */
#define SATA_SEP_ATTN        0x67 /* for all SEP command             */

/* I2C command type for SEP device */
#define I2C_CT_D2H_SAFTE     0x00 /* SEP-to-Host SAFTE data transfer */
#define I2C_CT_H2D_SAFTE     0x80 /* Host-to-SEP SAFTE data transfer */
#define I2C_CT_D2H_SES       0x02 /* SEP-to-Host SES data transfer   */
#define I2C_CT_H2D_SES       0x82 /* Host-to-SEP SES data transfer   */

/* command type flag */
#define I2C_CT_H2D           0x80

/* macro for judge H2D/D2H command type */
#define mis_i2c_ct_d2h(ct)    (!((ct) & I2C_CT_H2D))


/* SEP command */
#define I2C_CMD_IDENTIFY_SEP 0xEC /* identify sep                    */

/* IDENDIFY SEP data page definitions */
typedef struct IDENTIFY_SEP_DATA_
{
   MV_U8       dataLength;
   MV_U8       subenclosureID;
   MV_U8       logicalID[8];
   MV_U8       vendorID[8];
   MV_U8       productID[16];
   MV_U8       revisionLevel[4];
   MV_U8       channelID;
   MV_U8       firmwareRevisionLevel[4];
   MV_U8       interfaceIDstring[6];
   MV_U8       interfaceRevisionLevel[4];
   MV_U8       vendorSpecific[11];
} IDENTIFY_SEP_DATA, *PIDENTIFY_SEP_DATA;