core_inter.h

6440linuxDriver的源代码

#if !defined(CORE_MAIN_H)
#define CORE_MAIN_H

#if defined(_OS_LINUX) || defined(__QNXNTO__)
#   include "core_header.h"
#else
#   include "mv_include.h"
#endif /* defined(_OS_LINUX) || defined(__QNXNTO__) */

enum {
	CORE_STATE_ZOMBIE = 13,
	CORE_STATE_IDLE = 0,
	CORE_STATE_STARTED,
};

#ifdef SUPPORT_I2C
typedef struct _Domain_I2cLink
{
	MV_U8 I2C_State;
	MV_U8 I2C_Clock;
	MV_U16 I2cCmdFrameLen;
	MV_PVOID pI2cRequest;
	MV_U16 I2cRspFrameLen;
	MV_U16 I2cXferCount;
	MV_U8 I2cSEP_Address;
	MV_U8 I2cCmdHeader[8];
	MV_U8 I2cIdentify[64];
	PDomain_Device	pI2cDevice;
}Domain_I2cLink, *PDomain_I2cLink;
#endif //#ifdef SUPPORT_I2C

#ifdef SUPPORT_SGPIO
typedef struct _Domain_SGPIO
{
	MV_U8 Data_In_Low[8];
	MV_U8 Data_In_High[8];
	MV_U32 CRC;
}Domain_SGPIO, *PDomain_SGPIO;
#endif

/* must be 64-bit aligned */
struct _Core_Driver_Extension
{
	MV_LPVOID	Mmio_Base;						/* Memory IO base address */
#if __MM_SE__	
	struct mv_mod_desc *desc;
#endif /* __MM_SE__ */	
	MV_U16		Vendor_Id;
	MV_U16		Device_Id;
	MV_U8		State;
	MV_U8		Revision_Id;
	MV_U8		Phy_Num;						/* How much phy ports we have? */
	MV_U8		Reserved0;

	MV_U32		Capacity;						
	MV_U8		Port_Num;						/* How much ports we have? */
	MV_U8		SATA_Port_Num;
	MV_U8		MaxRegisterSet;
	MV_U8		Adapter_State;					/* Adatper state */

	MV_U8		Is_Dump;						/* Is during dump */
	MV_U8		Resetting;
#ifdef _OS_BIOS
	MV_U8		host_reseting;
#else
	MV_U8		Reserved1;
#endif
	MV_U16		Max_Io;
	MV_U8		PD_Count_Supported;
	MV_U8		Expander_Count_Supported;

	MV_U16		Slot_Count_Supported;
	MV_U8		Scratch_Count1;					/* used for core API purposes */
	MV_U8		Scratch_Count2;					/* used for core API purposes */

	MV_LPVOID			Base_Address[MAX_BASE_ADDRESS];	/* Base Address */
	Domain_Port			Ports[MAX_PORT_NUMBER];			/* Domain Ports */
	/* Because we are supporting performance mode, */
	/* we cannot use array for Domain_Device */
	/* user pointer, remember to allocate continuous memory for it */
	Domain_Device		*Devices;
	Domain_Expander		*Expanders;
#ifdef SUPPORT_PM
	Domain_PM			*PMs;
#endif

	/* new shared Device_Map system:
	   0 to MAX_DEVICE_ID-1 for drives,
	   MAX_DEVICE_ID to MAX_EXPANDER_ID-1 for expanders
	   MAX_EXPANDER_ID to MAX_PM_ID-1 for PM
	*/
#ifdef SUPPORT_PM
	MV_U8				Device_Map[MAX_PM_ID];
#else
	MV_U8				Device_Map[MAX_EXPANDER_ID];	
#endif
	MV_U8				Port_Map[MAX_PORT_ID];

	PMV_Request			*Running_Req;
	MV_U32				Running_Slot[16];
	MV_U32				Resetting_Slot[16];
	MV_U32				Completing_Slot[16];

	MV_U16		Current_Device_Id;				/* what device ID to assign next */
	MV_U8		Current_Expander_Id;				/* what target ID to assign next */
	MV_U8		MaxCmdSlotWidth;				/* 9 for 512, 10 for 1024 */

#ifdef SUPPORT_PM
	MV_U8		Current_PM_Id;
	MV_U8		PM_Count_Supported;
	MV_U8		Reserved2[2];
#endif

	List_Head	Waiting_List; 					/* Waiting Request Queue */
	List_Head	Complete_List;					/* Completed Request Queue */
#if !__MM_SE__
	List_Head	Internal_Req_List;				/* list of free internal requests */
#endif /* !__MM_SE__ */
#ifdef CORE_SAS_SUPPORT_ATA_COMMAND
	List_Head	Context_List;					/* list of core context data structure */
#endif
	List_Head	SATA_Scratch_List;			/* list of free scratch buffers for SATA */
	List_Head	SMP_Scratch_List;				/* list of free scratch buffers for SMP Requests */

	MV_PVOID        req_pool; /* internal request pool */

	OSSW_DECLARE_TIMER(timer);
	OSSW_DECLARE_SPINLOCK(lock);

	List_Head	SG_Buffer_List;				/* list of SG buffers for command table and XOR */
#ifdef SUPPORT_LARGE_REQUEST
 	/* To support large block request, we need many kinds of resources
 	 * including MV_Request, SG Table, Sense Buffer, Request context.
 	 * SG Table and Sense Buffer are assigned directly to sub MV_Request.
 	 * Request Context is shared with other requests and allocated on the fly. So far it's not used.
 	 * Decided not to use Internal_Req_List for sub request to avoid internal request starving.*/
 	List_Head	Sub_Req_List;				/* list of MV_Request used for sub request. */
 	MV_U16		Sub_Req_Count;
 	MV_U16		Reserved5;
#endif /* SUPPORT_LARGE_REQUEST */

#ifdef SUPPORT_CONSOLIDATE
	PConsolidate_Extension	pConsolid_Extent;
	PConsolidate_Device     pConsolid_Device;
#endif
	MV_PVOID Cmd_List;			/* Can be PMV_PATA_Command_Header or PMV_Command_Header */
	MV_PHYSICAL_ADDR Cmd_List_DMA;

	/* Received FIS */
	MV_PVOID RX_FIS;
	MV_PHYSICAL_ADDR RX_FIS_DMA;

	/* The 32 command tables. */
	MV_PVOID Cmd_Table;
	MV_PHYSICAL_ADDR Cmd_Table_DMA;

	/* Delivery Queue */
	MV_PVOID DELV_Q_;
	MV_PHYSICAL_ADDR DELV_Q_DMA;

	/* Completion Queue */
	MV_PVOID CMPL_Q;
	MV_PHYSICAL_ADDR CMPL_Q_DMA;

	MV_PVOID pDiscoverBuffer;
	MV_U16 LastDELV_Q;
	MV_U16 LastCMPL_Q;
	MV_U8  Reserved3[4];

	/* Command List Slot Number Pool*/
	Tag_Stack Tag_Pool;
	Tag_Stack Device_Pool;
	Tag_Stack Expander_Pool;
	Tag_Stack PM_Pool;
	Tag_Stack Port_Pool;
#ifdef SUPPORT_I2C
	Domain_I2cLink I2cLink;
#endif
#ifdef SUPPORT_SGPIO
	Domain_SGPIO SGPIO_Result;
#endif
#ifndef SOFTWARE_XOR
/*--XOR--------------------------------------------------*/
	MV_PVOID XOR_Cmd_List;			
	MV_PHYSICAL_ADDR XOR_Cmd_List_DMA;

	/* The 32 command tables. */
	MV_PVOID XOR_Cmd_Table;
	MV_PHYSICAL_ADDR XOR_Cmd_Table_DMA;

#ifdef RAID6_HARDWARE_XOR
	List_Head	XOR_Table_List;			/* a list of XOR_Table_Wrapper */
	List_Head	XOR_Context_List;
#endif

	/* Delivery Queue */
	MV_PVOID XOR_DELV_Q;
	MV_PHYSICAL_ADDR XOR_DELV_Q_DMA;

	/* Completion Queue */
	MV_PVOID XOR_CMPL_Q;
	MV_PHYSICAL_ADDR XOR_CMPL_Q_DMA;

	MV_U16 XOR_LastDELV_Q;
	MV_U16 XOR_LastCMPL_Q;

	PMV_XOR_Request *XOR_Running_Req;
	List_Head		XOR_Waiting_List;
	MV_U16			XOR_Req_Count;
	MV_U16 Reserved4;

	/* Command List Slot Number Pool*/
	Tag_Stack XOR_Tag_Pool;
#endif
	/* Phy info */
	Domain_Phy Phy[MAX_PORT_NUMBER];

};

#endif /* CORE_MAIN_H */