sensorstream.ldf

Sensor Stream for BF561

}
MEM_B_L1_DATA_A   {		/* L1 Data Bank A SRAM - 16K */
	TYPE(RAM) WIDTH(8)
	START(0xFF400000) END(0xFF403FFF)
}
#else  /* } { DATAA_CACHE */
MEM_B_L1_DATA_A   {		/* L1 Data Bank A SRAM - 32K */
	TYPE(RAM) WIDTH(8)
	START(0xFF400000) END(0xFF407FFF)
}
#endif /* } DATAA_CACHE */

/* L2 SRAM - 128K. */
/* For convenience, we divide this space into: */
/* Core B only - 32K */
/* Core A only - 32K */
/* Shared = 64K */
/* And then subdivide each core-only area for program layout. */

/* Core B only - FEB00000 to FEB07FFF */
#ifdef IDDE_ARGS /* { */
#define ARGV_START 0xFEB07F00
MEM_ARGV_B     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB07F00) END(0xFEB07FFF)
}
#ifndef USE_CACHE /* { */
MEM_L2_HEAP_B     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB04000) END(0xFEB07EFF)
}
MEM_L2_SRAM_B     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB00000) END(0xFEB03FFF)
}
#else /* } USE_CACHE { */
MEM_L2_SRAM_B     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB00000) END(0xFEB07EFF)
}
#endif /* } USE_CACHE */
#else
#ifndef USE_CACHE /* { */
MEM_L2_HEAP_B     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB04000) END(0xFEB07FFF)
}
MEM_L2_SRAM_B     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB00000) END(0xFEB03FFF)
}
#else /* } USE_CACHE { */
MEM_L2_SRAM_B     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB00000) END(0xFEB07FFF)
}
#endif /* } USE_CACHE */
#endif /* IDDE_ARGS } */
/* Core A only - FEB08000 to FEB0FFFF */
#ifdef IDDE_ARGS /* { */
#ifndef ARGV_START
#define ARGV_START 0xFEB0FF00
#endif
MEM_ARGV_A     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB0FF00) END(0xFEB0FFFF)
}
#ifndef USE_CACHE /* { */
MEM_L2_HEAP_A     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB0C000) END(0xFEB0FEFF)
}
MEM_L2_SRAM_A     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB08000) END(0xFEB0BFFF)
}
#else /* } USE_CACHE { */
MEM_L2_SRAM_A     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB08000) END(0xFEB0FEFF)
}
#endif /* } USE_CACHE */
#else
#ifndef USE_CACHE
MEM_L2_HEAP_A     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB0C000) END(0xFEB0FFFF)
}
MEM_L2_SRAM_A     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB08000) END(0xFEB0BFFF)
}
#else /* } USE_CACHE { */
MEM_L2_SRAM_A     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB08000) END(0xFEB0FFFF)
}
#endif /* } USE_CACHE */
#endif /* IDDE_ARGS } */
/* Shared L2 */
MEM_L2_SRAM    { START(0xFEB10000) END(0xFEB1FFFF) TYPE(RAM) WIDTH(8) }
 /* Async Memory in Banks of 64 MB */
MEM_ASYNC3     { START(0x2C000000) END(0x2FFFFFFF) TYPE(RAM) WIDTH(8) }
MEM_ASYNC2     { START(0x28000000) END(0x2BFFFFFF) TYPE(RAM) WIDTH(8) }
MEM_ASYNC1     { START(0x24000000) END(0x27FFFFFF) TYPE(RAM) WIDTH(8) }
MEM_ASYNC0     { START(0x20000000) END(0x23FFFFFF) TYPE(RAM) WIDTH(8) }

/* SDRAM Partitioning:
   SDRAM for BF561 is available in up to 128MB in 4 External Banks.
   Each external bank consists of 4 internal banks.
   The EBUI SDRAM Controller can hold open up to 4 internal banks 
   open synchronously. Suitable partitioning that avoids placing
   data and program in the same internal bank can improve performance.
   The default LDF contains a configuration for two external banks
   each holding 32MB SDRAM. The default LDF uses one bank per core,
   partitioned to segment data and program.
  */

  /* Bank usage:
        Bank 0 - 8MB/core - Heap 
        Bank 1 - 8MB/core - Data
        Bank 2 - 8MB/core - Data/BSZ
        Bank 3 - 8MB Core A, 4MB Core B - Program
                             4MB shared - misc
  */
#if !defined(PARTITION_EZKIT_SDRAM)
# define PARTITION_EZKIT_SDRAM
#endif
  /* Core A */
MEM_SDRAM0_BANK0     { START(0x00000004) END(0x00FFFFFF) TYPE(RAM) WIDTH(8) }
MEM_SDRAM0_BANK1     { START(0x01000000) END(0x01FFFFFF) TYPE(RAM) WIDTH(8) }
MEM_SDRAM0_BANK2     { START(0x02000000) END(0x02FFFFFF) TYPE(RAM) WIDTH(8) }
MEM_SDRAM0_BANK3     { START(0x03000000) END(0x03FFFFFF) TYPE(RAM) WIDTH(8) }
  /* Core B */
//MEM_SDRAM1_BANK0     { START(0x02000000) END(0x027FFFFF) TYPE(RAM) WIDTH(8) }
//MEM_SDRAM1_BANK1     { START(0x02800000) END(0x02FFFFFF) TYPE(RAM) WIDTH(8) }
//MEM_SDRAM1_BANK2     { START(0x03000000) END(0x037FFFFF) TYPE(RAM) WIDTH(8) }
//MEM_SDRAM1_BANK3     { START(0x03800000) END(0x03CFFFFF) TYPE(RAM) WIDTH(8) }
 /* shared srdam */
//MEM_SDRAM1_SHARED    { START(0x03D00000) END(0x03FFFFFF) TYPE(RAM) WIDTH(8) }
}

/* Core A */
PROCESSOR p0
{
    OUTPUT( $COMMAND_LINE_OUTPUT_DIRECTORY/p0.dxe )

    /* Following address must match start of MEM_A_L1_CODE */
    RESOLVE(start,0xFFA00000)
#ifdef IDDE_ARGS
    RESOLVE(___argv_string,ARGV_START)
#endif
    KEEP(start,_main)

    SECTIONS
    {
#if defined(__WORKAROUND_AVOID_LDF_BLOCK_BOUNDARIES) /* { */
    /* Workaround for hardware errata 05-00-0189 -
    ** "Speculative (and fetches made at boundary of reserved memory
    ** space) for instruction or data fetches may cause false
    ** protection exceptions".
    **
    ** Done by avoiding use of 76 bytes from at the end of blocks
    ** that are adjacent to reserved memory. Workaround is enabled
    ** for appropriate silicon revisions (-si-revision switch).
    */
    RESERVE(___waba0=0xFFB00FFF - 75,___la0=76)   /* scratchpad */
#  if !INSTR_CACHE
    RESERVE(___waba1=0xFFA13FFF - 75,___la1=76)   /* l1 instr sram/cache */
#  endif
    RESERVE(___waba2=0xFFA03FFF - 75,___la2=76)   /* l1 instr sram */
#  if DATAB_CACHE
    RESERVE(___waba3=0xFF903FFF - 75,___la3=76)   /* data B sram */
#  else
    RESERVE(___waba4=0xFF907FFF - 75,___la4=76)   /* data B sram/cache */
#  endif
#  if DATAA_CACHE
    RESERVE(___waba5=0xFF803FFF - 75,___la5=76)   /* data A sram */
#  else
    RESERVE(___waba6=0xFF807FFF - 75,___la6=76)   /* data A sram/cache */
#  endif
    RESERVE(___waba7=0xFEB1FFFF - 75,___la7=76)   /* L2 sram */
    RESERVE(___waba8=0x2FFFFFFF - 75,___la8=76)   /* async bank 3 */
#  if defined(PARTITION_EZKIT_SDRAM)
    RESERVE(___waba9=0x3FFFFFF - 75,___la9=76)    /* EZ-Kit 64MB sdram */
#  elif defined(USE_CACHE) || defined(USE_SDRAM)
    RESERVE(___waba10=0x7FFFFFF - 75,___la10=76)  /* sdram 218MB */
#  endif
#else 
    /* FEB1FC00->FEB1FFFF : Reseved in boot Phase for 2nd stage boot loader */
    RESERVE(___ssld=0xFEB1FC00,___lssld=0x400) 
#endif /*} __WORKAROUND_AVOID_LDF_BLOCK_BOUNDARIES */


        l1_code {
            INPUT_SECTION_ALIGN(4)
            __CORE = 0;
            INPUT_SECTIONS( $OBJECTS(L1_code) $LIBRARIES(L1_code))
            INPUT_SECTIONS( $OBJECTS(cplb) $LIBRARIES(cplb))
            INPUT_SECTIONS( $OBJECTS(cplb_code) $LIBRARIES(cplb_code))
            INPUT_SECTIONS( $OBJECTS(noncache_code) $LIBRARIES(noncache_code))
            INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program))
        } >MEM_A_L1_CODE

        l1_code_cache {
#if INSTR_CACHE /* { */
            ___l1_code_cache = 1;
#else
            ___l1_code_cache = 0;
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(L1_code) $LIBRARIES(L1_code))
            INPUT_SECTIONS( $OBJECTS(cplb) $LIBRARIES(cplb))
            INPUT_SECTIONS( $OBJECTS(cplb_code) $LIBRARIES(cplb_code))
            INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program))
#endif /* INSTR_CACHE } */
        } >MEM_A_L1_CODE_CACHE

#if DATAA_CACHE /* { */
        l1_data_a_cache {
            INPUT_SECTION_ALIGN(4)
            ___l1_data_cache_a = 1;
        } >MEM_A_L1_DATA_A_CACHE
#endif /* DATAA_CACHE } */

        l1_data_a {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(L1_data_a) $LIBRARIES(L1_data_a))
#if !DATAA_CACHE /* { */
            ___l1_data_cache_a = 0;
#endif /* DATAA_CACHE } */
            INPUT_SECTIONS( $OBJECTS(cplb_data) $LIBRARIES(cplb_data))
            INPUT_SECTIONS( $OBJECTS(voldata) $LIBRARIES(voldata))
            INPUT_SECTIONS( $OBJECTS(data1) $LIBRARIES(data1))
#if defined(__cplusplus) || defined(USER_CRT)   /* { */
            INPUT_SECTIONS( $OBJECTS(.edt) $LIBRARIES(.edt) )
            INPUT_SECTIONS( $OBJECTS(.cht) $LIBRARIES(.cht) )
#endif
            INPUT_SECTIONS( $OBJECTS(constdata) $LIBRARIES(constdata))
        } >MEM_A_L1_DATA_A

        bsz_L1_data_a ZERO_INIT {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(bsz) $LIBRARIES(bsz))
        } >MEM_A_L1_DATA_A

#if DATAB_CACHE /* { */
        l1_data_b_cache {
            INPUT_SECTION_ALIGN(4)
            ___l1_data_cache_b = 1;
        } >MEM_A_L1_DATA_B_CACHE
#endif /* DATAB_CACHE } */

        l1_data_b {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(L1_data_b) $LIBRARIES(L1_data_b))
#if !DATAB_CACHE /* { */
            ___l1_data_cache_b = 0;
#endif /* DATAB_CACHE } */
#if defined(__cplusplus) || defined(USER_CRT)   /* { */
            INPUT_SECTIONS( $OBJECTS(ctor) $LIBRARIES(ctor) )
            INPUT_SECTIONS( $OBJECTS(ctorl) $LIBRARIES(ctorl) )
            INPUT_SECTIONS( $OBJECTS(.gdt) $LIBRARIES(.gdt) )
            INPUT_SECTIONS( $OBJECTS(.gdtl) $LIBRARIES(.gdtl) )
            INPUT_SECTIONS( $OBJECTS(vtbl) $LIBRARIES(vtbl) )
            INPUT_SECTIONS( $OBJECTS(.frt) $LIBRARIES(.frt) )
            INPUT_SECTIONS( $OBJECTS(.frtl) $LIBRARIES(.frtl) )
#endif	/* } */
            INPUT_SECTIONS( $OBJECTS(data1) $LIBRARIES(data1))
            INPUT_SECTIONS( $OBJECTS(cplb_data) $LIBRARIES(cplb_data))
            INPUT_SECTIONS( $OBJECTS(voldata) $LIBRARIES(voldata))
            INPUT_SECTIONS( $OBJECTS(constdata) $LIBRARIES(constdata))
#if defined(__cplusplus) || defined(USER_CRT)   /* { */
            INPUT_SECTIONS( $OBJECTS(.edt) $LIBRARIES(.edt) )
            INPUT_SECTIONS( $OBJECTS(.cht) $LIBRARIES(.cht) )
#endif
        } >MEM_A_L1_DATA_B

        bsz_L1_data_b ZERO_INIT {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(bsz) $LIBRARIES(bsz))
            
        } >MEM_A_L1_DATA_B

        l2_sram_a {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(L2_sram_a) $LIBRARIES(L2_sram_a))
            INPUT_SECTIONS( $OBJECTS(noncache_code) $LIBRARIES(noncache_code))
            INPUT_SECTIONS( $OBJECTS(bsz_init) $LIBRARIES(bsz_init))
#if defined(__ADI_MULTICORE) /* { */
             INPUT_SECTIONS( $OBJECTS(mc_data) $LIBRARIES(mc_data))
#endif /* __ADI_MULTICORE } */
            INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program))
            INPUT_SECTIONS( $OBJECTS(cplb) $LIBRARIES(cplb))
            INPUT_SECTIONS( $OBJECTS(cplb_code) $LIBRARIES(cplb_code))
            INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
            INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
            INPUT_SECTIONS( $OBJECTS(cplb_data) $LIBRARIES(cplb_data))
#if defined(__cplusplus) || defined(USER_CRT)   /* { */
            INPUT_SECTIONS( $OBJECTS(.edt) $LIBRARIES(.edt) )
            INPUT_SECTIONS( $OBJECTS(.cht) $LIBRARIES(.cht) )
#endif /* } */
            INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
        } >MEM_L2_SRAM_A
      //  .meminit { ALIGN(4) } >MEM_L2_SRAM_A

        bsz_L2_sram_a ZERO_INIT {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(bsz) $LIBRARIES(bsz))
        } >MEM_L2_SRAM_A

        stack {
            ldf_stack_space = .;
            ldf_stack_end = ldf_stack_space + MEMORY_SIZEOF(MEM_A_L1_STACK);
        } >MEM_A_L1_STACK

#ifndef USE_CACHE
        heap {
            // Allocate a heap for the application
            ldf_heap_space = .;
            ldf_heap_end = ldf_heap_space + MEMORY_SIZEOF(MEM_L2_HEAP_A) - 1;
            ldf_heap_length = ldf_heap_end - ldf_heap_space;        
        } >MEM_L2_HEAP_A
#else
        heap {
            // Allocate a heap for the application
            ldf_heap_space = .;
            ldf_heap_end = ldf_heap_space + MEMORY_SIZEOF(MEM_SDRAM0_BANK0) - 1;
            ldf_heap_length = ldf_heap_end - ldf_heap_space;        
        } >MEM_SDRAM0_BANK0
#endif

        l2_shared {
            // Contains data shared between cores - Requires use of resolve.
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $LIBRARIES(l2_shared) )
            // Holds control variable used to ensure atomic file I/O
            // Must be in shared memory and NOT cached.
            INPUT_SECTIONS( $LIBRARIES(primio_atomic_lock))
        } >MEM_L2_SRAM
        
        sdram0_bank0 {
          // Data
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS($OBJECTS(sdram_bank0) $LIBRARIES(sdram_bank0))
       } >MEM_SDRAM0_BANK0

        sdram0_bank1 {
          // Data
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS($OBJECTS(sdram_bank1) $LIBRARIES(sdram_bank1))
          INPUT_SECTIONS($OBJECTS(sdram_data) $LIBRARIES(sdram_data))
          INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
          INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
        } >MEM_SDRAM0_BANK1

        sdram0_bank2 {
          // Data
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS($OBJECTS(sdram0) $LIBRARIES(sdram0))
          INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
        } > MEM_SDRAM0_BANK2

        sdram0_bank2_bsz ZERO_INIT {
          // Bsz
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz))
        } > MEM_SDRAM0_BANK2

        sdram0_bank3 {
          // Program Section
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS($OBJECTS(sdram_bank3) $LIBRARIES(sdram_bank3))
          INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program))
          INPUT_SECTIONS( $OBJECTS(noncache_code) $LIBRARIES(noncache_code))
        } >MEM_SDRAM0_BANK3

    }
}

/* Core B 
 * CoreB_Idle is a small program to keep Core B at IDLE so PLL can be programmed on CoreA
*/

//$OBJECTS_COREB = $ADI_DSP/Blackfin/EZ-KITs/ADSP-BF561/Utilities/CoreB_Idle.doj;
//$OBJECTS_COREB = CoreB_Idle.doj;
$OBJECTS_COREB = ../../../BFinUtils/ADSP-BF561/SDK-CoreB_Idle.doj;

PROCESSOR p1
{
    OUTPUT( $COMMAND_LINE_OUTPUT_DIRECTORY/p1.dxe )

    /* Following address must match start of MEM_B_L1_PROGRAM */
    RESOLVE(start,0xFF600000)
    KEEP(start)

    SECTIONS 
    {
        l1_code_cache {
            INPUT_SECTION_ALIGN(4)
            __CORE = 1;
            INPUT_SECTIONS( $OBJECTS_COREB(program))
        } >MEM_B_L1_CODE
    }

}