myfx2.tan.qmsg

FPGA与USB通信的测试代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "MMCLK register register DREG\[0\] DREG\[15\] 275.03 MHz Internal " "Info: Clock \"MMCLK\" Internal fmax is restricted to 275.03 MHz between source register \"DREG\[0\]\" and destination register \"DREG\[15\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.536 ns + Longest register register " "Info: + Longest register to register delay is 2.536 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DREG\[0\] 1 REG LC_X2_Y15_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y15_N2; Fanout = 4; REG Node = 'DREG\[0\]'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "" { DREG[0] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.533 ns) + CELL(0.564 ns) 1.097 ns DREG\[0\]~129 2 COMB LC_X2_Y15_N2 2 " "Info: 2: + IC(0.533 ns) + CELL(0.564 ns) = 1.097 ns; Loc. = LC_X2_Y15_N2; Fanout = 2; COMB Node = 'DREG\[0\]~129'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "1.097 ns" { DREG[0] DREG[0]~129 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.175 ns DREG\[1\]~133 3 COMB LC_X2_Y15_N3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.175 ns; Loc. = LC_X2_Y15_N3; Fanout = 2; COMB Node = 'DREG\[1\]~133'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "0.078 ns" { DREG[0]~129 DREG[1]~133 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.353 ns DREG\[2\]~137 4 COMB LC_X2_Y15_N4 6 " "Info: 4: + IC(0.000 ns) + CELL(0.178 ns) = 1.353 ns; Loc. = LC_X2_Y15_N4; Fanout = 6; COMB Node = 'DREG\[2\]~137'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "0.178 ns" { DREG[1]~133 DREG[2]~137 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.561 ns DREG\[7\]~157 5 COMB LC_X2_Y15_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.208 ns) = 1.561 ns; Loc. = LC_X2_Y15_N9; Fanout = 6; COMB Node = 'DREG\[7\]~157'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "0.208 ns" { DREG[2]~137 DREG[7]~157 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.697 ns DREG\[12\]~177 6 COMB LC_X2_Y14_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.697 ns; Loc. = LC_X2_Y14_N4; Fanout = 3; COMB Node = 'DREG\[12\]~177'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "0.136 ns" { DREG[7]~157 DREG[12]~177 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.536 ns DREG\[15\] 7 REG LC_X2_Y14_N7 2 " "Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 2.536 ns; Loc. = LC_X2_Y14_N7; Fanout = 2; REG Node = 'DREG\[15\]'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "0.839 ns" { DREG[12]~177 DREG[15] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.003 ns 78.98 % " "Info: Total cell delay = 2.003 ns ( 78.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.533 ns 21.02 % " "Info: Total interconnect delay = 0.533 ns ( 21.02 % )" {  } {  } 0}  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "2.536 ns" { DREG[0] DREG[0]~129 DREG[1]~133 DREG[2]~137 DREG[7]~157 DREG[12]~177 DREG[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.536 ns" { DREG[0] DREG[0]~129 DREG[1]~133 DREG[2]~137 DREG[7]~157 DREG[12]~177 DREG[15] } { 0.000ns 0.533ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.509 ns - Smallest " "Info: - Smallest clock skew is -0.509 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MMCLK destination 7.249 ns + Shortest register " "Info: + Shortest clock path from clock \"MMCLK\" to destination register is 7.249 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MMCLK 1 CLK PIN_153 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 2; CLK Node = 'MMCLK'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "" { MMCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.358 ns) + CELL(0.935 ns) 5.762 ns CLK_2 2 REG LC_X3_Y14_N4 20 " "Info: 2: + IC(3.358 ns) + CELL(0.935 ns) = 5.762 ns; Loc. = LC_X3_Y14_N4; Fanout = 20; REG Node = 'CLK_2'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "4.293 ns" { MMCLK CLK_2 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.711 ns) 7.249 ns DREG\[15\] 3 REG LC_X2_Y14_N7 2 " "Info: 3: + IC(0.776 ns) + CELL(0.711 ns) = 7.249 ns; Loc. = LC_X2_Y14_N7; Fanout = 2; REG Node = 'DREG\[15\]'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "1.487 ns" { CLK_2 DREG[15] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.97 % " "Info: Total cell delay = 3.115 ns ( 42.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.134 ns 57.03 % " "Info: Total interconnect delay = 4.134 ns ( 57.03 % )" {  } {  } 0}  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "7.249 ns" { MMCLK CLK_2 DREG[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.249 ns" { MMCLK MMCLK~out0 CLK_2 DREG[15] } { 0.000ns 0.000ns 3.358ns 0.776ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MMCLK source 7.758 ns - Longest register " "Info: - Longest clock path from clock \"MMCLK\" to source register is 7.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MMCLK 1 CLK PIN_153 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 2; CLK Node = 'MMCLK'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "" { MMCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.358 ns) + CELL(0.935 ns) 5.762 ns CLK_2 2 REG LC_X3_Y14_N4 20 " "Info: 2: + IC(3.358 ns) + CELL(0.935 ns) = 5.762 ns; Loc. = LC_X3_Y14_N4; Fanout = 20; REG Node = 'CLK_2'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "4.293 ns" { MMCLK CLK_2 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.285 ns) + CELL(0.711 ns) 7.758 ns DREG\[0\] 3 REG LC_X2_Y15_N2 4 " "Info: 3: + IC(1.285 ns) + CELL(0.711 ns) = 7.758 ns; Loc. = LC_X2_Y15_N2; Fanout = 4; REG Node = 'DREG\[0\]'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "1.996 ns" { CLK_2 DREG[0] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 40.15 % " "Info: Total cell delay = 3.115 ns ( 40.15 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.643 ns 59.85 % " "Info: Total interconnect delay = 4.643 ns ( 59.85 % )" {  } {  } 0}  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "7.758 ns" { MMCLK CLK_2 DREG[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.758 ns" { MMCLK MMCLK~out0 CLK_2 DREG[0] } { 0.000ns 0.000ns 3.358ns 1.285ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "7.249 ns" { MMCLK CLK_2 DREG[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.249 ns" { MMCLK MMCLK~out0 CLK_2 DREG[15] } { 0.000ns 0.000ns 3.358ns 0.776ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "7.758 ns" { MMCLK CLK_2 DREG[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.758 ns" { MMCLK MMCLK~out0 CLK_2 DREG[0] } { 0.000ns 0.000ns 3.358ns 1.285ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0}  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "2.536 ns" { DREG[0] DREG[0]~129 DREG[1]~133 DREG[2]~137 DREG[7]~157 DREG[12]~177 DREG[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.536 ns" { DREG[0] DREG[0]~129 DREG[1]~133 DREG[2]~137 DREG[7]~157 DREG[12]~177 DREG[15] } { 0.000ns 0.533ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } } { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "7.249 ns" { MMCLK CLK_2 DREG[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.249 ns" { MMCLK MMCLK~out0 CLK_2 DREG[15] } { 0.000ns 0.000ns 3.358ns 0.776ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "7.758 ns" { MMCLK CLK_2 DREG[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.758 ns" { MMCLK MMCLK~out0 CLK_2 DREG[0] } { 0.000ns 0.000ns 3.358ns 1.285ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "" { DREG[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { DREG[15] } {  } {  } } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "MMCLK GPD\[4\] DREG\[4\] 13.214 ns register " "Info: tco from clock \"MMCLK\" to destination pin \"GPD\[4\]\" through register \"DREG\[4\]\" is 13.214 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MMCLK source 7.758 ns + Longest register " "Info: + Longest clock path from clock \"MMCLK\" to source register is 7.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MMCLK 1 CLK PIN_153 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 2; CLK Node = 'MMCLK'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "" { MMCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.358 ns) + CELL(0.935 ns) 5.762 ns CLK_2 2 REG LC_X3_Y14_N4 20 " "Info: 2: + IC(3.358 ns) + CELL(0.935 ns) = 5.762 ns; Loc. = LC_X3_Y14_N4; Fanout = 20; REG Node = 'CLK_2'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "4.293 ns" { MMCLK CLK_2 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.285 ns) + CELL(0.711 ns) 7.758 ns DREG\[4\] 3 REG LC_X2_Y15_N6 4 " "Info: 3: + IC(1.285 ns) + CELL(0.711 ns) = 7.758 ns; Loc. = LC_X2_Y15_N6; Fanout = 4; REG Node = 'DREG\[4\]'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "1.996 ns" { CLK_2 DREG[4] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 40.15 % " "Info: Total cell delay = 3.115 ns ( 40.15 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.643 ns 59.85 % " "Info: Total interconnect delay = 4.643 ns ( 59.85 % )" {  } {  } 0}  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "7.758 ns" { MMCLK CLK_2 DREG[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.758 ns" { MMCLK MMCLK~out0 CLK_2 DREG[4] } { 0.000ns 0.000ns 3.358ns 1.285ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.232 ns + Longest register pin " "Info: + Longest register to pin delay is 5.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DREG\[4\] 1 REG LC_X2_Y15_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y15_N6; Fanout = 4; REG Node = 'DREG\[4\]'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "" { DREG[4] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.124 ns) + CELL(2.108 ns) 5.232 ns GPD\[4\] 2 PIN PIN_63 0 " "Info: 2: + IC(3.124 ns) + CELL(2.108 ns) = 5.232 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'GPD\[4\]'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "5.232 ns" { DREG[4] GPD[4] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 40.29 % " "Info: Total cell delay = 2.108 ns ( 40.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.124 ns 59.71 % " "Info: Total interconnect delay = 3.124 ns ( 59.71 % )" {  } {  } 0}  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "5.232 ns" { DREG[4] GPD[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.232 ns" { DREG[4] GPD[4] } { 0.000ns 3.124ns } { 0.000ns 2.108ns } } }  } 0}  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "7.758 ns" { MMCLK CLK_2 DREG[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.758 ns" { MMCLK MMCLK~out0 CLK_2 DREG[4] } { 0.000ns 0.000ns 3.358ns 1.285ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "5.232 ns" { DREG[4] GPD[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.232 ns" { DREG[4] GPD[4] } { 0.000ns 3.124ns } { 0.000ns 2.108ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "MMCLK USBCLK 5.957 ns Longest " "Info: Longest tpd from source pin \"MMCLK\" to destination pin \"USBCLK\" is 5.957 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MMCLK 1 CLK PIN_153 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 2; CLK Node = 'MMCLK'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "" { MMCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.364 ns) + CELL(2.124 ns) 5.957 ns USBCLK 2 PIN PIN_124 0 " "Info: 2: + IC(2.364 ns) + CELL(2.124 ns) = 5.957 ns; Loc. = PIN_124; Fanout = 0; PIN Node = 'USBCLK'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "4.488 ns" { MMCLK USBCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 44 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.593 ns 60.32 % " "Info: Total cell delay = 3.593 ns ( 60.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.364 ns 39.68 % " "Info: Total interconnect delay = 2.364 ns ( 39.68 % )" {  } {  } 0}  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "5.957 ns" { MMCLK USBCLK } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.957 ns" { MMCLK MMCLK~out0 USBCLK } { 0.000ns 0.000ns 2.364ns } { 0.000ns 1.469ns 2.124ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 20 23:24:35 2006 " "Info: Processing ended: Wed Sep 20 23:24:35 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}