myfx2.tan.qmsg

FPGA与USB通信的测试代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 18 19:31:00 2006 " "Info: Processing started: Mon Sep 18 19:31:00 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off MYFX2 -c MYFX2 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off MYFX2 -c MYFX2 --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "PA\[3\] LED\[3\] 13.402 ns Longest " "Info: Longest tpd from source pin \"PA\[3\]\" to destination pin \"LED\[3\]\" is 13.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns PA\[3\] 1 PIN PIN_41 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_41; Fanout = 1; PIN Node = 'PA\[3\]'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "" { PA[3] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(9.809 ns) + CELL(2.124 ns) 13.402 ns LED\[3\] 2 PIN PIN_180 0 " "Info: 2: + IC(9.809 ns) + CELL(2.124 ns) = 13.402 ns; Loc. = PIN_180; Fanout = 0; PIN Node = 'LED\[3\]'" {  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "11.933 ns" { PA[3] LED[3] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.v" 34 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.593 ns 26.81 % " "Info: Total cell delay = 3.593 ns ( 26.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.809 ns 73.19 % " "Info: Total interconnect delay = 9.809 ns ( 73.19 % )" {  } {  } 0}  } { { "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" "" { Report "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/db/MYFX2.quartus_db" { Floorplan "C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/" "" "13.402 ns" { PA[3] LED[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.402 ns" { PA[3] PA[3]~out0 LED[3] } { 0.000ns 0.000ns 9.809ns } { 0.000ns 1.469ns 2.124ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 18 19:31:00 2006 " "Info: Processing ended: Mon Sep 18 19:31:00 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}