proj.tan.qmsg

基于QuartusII的LCD1602-Verilog 源代码

{ "Info" "ITDB_FULL_TCO_RESULT" "clk LCD_D\[5\] lcd:inst\|counter\[3\] 33.587 ns register " "Info: tco from clock \"clk\" to destination pin \"LCD_D\[5\]\" through register \"lcd:inst\|counter\[3\]\" is 33.587 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 15.303 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 15.303 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd_test.bdf" "" { Schematic "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.449 ns) + CELL(0.970 ns) 3.559 ns div16:inst1\|count\[3\] 2 REG LCFF_X15_Y6_N9 17 " "Info: 2: + IC(1.449 ns) + CELL(0.970 ns) = 3.559 ns; Loc. = LCFF_X15_Y6_N9; Fanout = 17; REG Node = 'div16:inst1\|count\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.419 ns" { clk div16:inst1|count[3] } "NODE_NAME" } } { "DIV16.v" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/DIV16.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.970 ns) 5.566 ns lcd:inst\|clkcnt\[5\] 3 REG LCFF_X18_Y6_N11 3 " "Info: 3: + IC(1.037 ns) + CELL(0.970 ns) = 5.566 ns; Loc. = LCFF_X18_Y6_N11; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.007 ns" { div16:inst1|count[3] lcd:inst|clkcnt[5] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.126 ns) + CELL(0.535 ns) 7.227 ns lcd:inst\|Equal0~148 4 COMB LCCOMB_X17_Y6_N16 1 " "Info: 4: + IC(1.126 ns) + CELL(0.535 ns) = 7.227 ns; Loc. = LCCOMB_X17_Y6_N16; Fanout = 1; COMB Node = 'lcd:inst\|Equal0~148'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.661 ns" { lcd:inst|clkcnt[5] lcd:inst|Equal0~148 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.614 ns) 8.230 ns lcd:inst\|Equal0 5 COMB LCCOMB_X17_Y6_N4 17 " "Info: 5: + IC(0.389 ns) + CELL(0.614 ns) = 8.230 ns; Loc. = LCCOMB_X17_Y6_N4; Fanout = 17; COMB Node = 'lcd:inst\|Equal0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.003 ns" { lcd:inst|Equal0~148 lcd:inst|Equal0 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.328 ns) + CELL(0.970 ns) 9.528 ns lcd:inst\|clkdiv 6 REG LCFF_X17_Y6_N7 3 " "Info: 6: + IC(0.328 ns) + CELL(0.970 ns) = 9.528 ns; Loc. = LCFF_X17_Y6_N7; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.298 ns" { lcd:inst|Equal0 lcd:inst|clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.451 ns) + CELL(0.970 ns) 11.949 ns lcd:inst\|clk_int 7 REG LCFF_X12_Y6_N23 2 " "Info: 7: + IC(1.451 ns) + CELL(0.970 ns) = 11.949 ns; Loc. = LCFF_X12_Y6_N23; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.421 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.866 ns) + CELL(0.000 ns) 13.815 ns lcd:inst\|clk_int~clkctrl 8 COMB CLKCTRL_G3 19 " "Info: 8: + IC(1.866 ns) + CELL(0.000 ns) = 13.815 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'lcd:inst\|clk_int~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.866 ns" { lcd:inst|clk_int lcd:inst|clk_int~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.822 ns) + CELL(0.666 ns) 15.303 ns lcd:inst\|counter\[3\] 9 REG LCFF_X13_Y6_N21 13 " "Info: 9: + IC(0.822 ns) + CELL(0.666 ns) = 15.303 ns; Loc. = LCFF_X13_Y6_N21; Fanout = 13; REG Node = 'lcd:inst\|counter\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.f