proj.tan.qmsg

基于QuartusII的LCD1602-Verilog 源代码

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 14 " "Warning: Circuit may not operate. Detected 14 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lcd:inst\|clk_int lcd:inst\|clk_int clk 475 ps " "Info: Found hold time violation between source  pin or register \"lcd:inst\|clk_int\" and destination pin or register \"lcd:inst\|clk_int\" for clock \"clk\" (Hold time is 475 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.974 ns + Largest " "Info: + Largest clock skew is 0.974 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.645 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd_test.bdf" "" { Schematic "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.449 ns) + CELL(0.970 ns) 3.559 ns div16:inst1\|count\[3\] 2 REG LCFF_X15_Y6_N9 17 " "Info: 2: + IC(1.449 ns) + CELL(0.970 ns) = 3.559 ns; Loc. = LCFF_X15_Y6_N9; Fanout = 17; REG Node = 'div16:inst1\|count\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.419 ns" { clk div16:inst1|count[3] } "NODE_NAME" } } { "DIV16.v" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/DIV16.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.970 ns) 5.566 ns lcd:inst\|clkcnt\[5\] 3 REG LCFF_X18_Y6_N11 3 " "Info: 3: + IC(1.037 ns) + CELL(0.970 ns) = 5.566 ns; Loc. = LCFF_X18_Y6_N11; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.007 ns" { div16:inst1|count[3] lcd:inst|clkcnt[5] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.126 ns) + CELL(0.535 ns) 7.227 ns lcd:inst\|Equal0~148 4 COMB LCCOMB_X17_Y6_N16 1 " "Info: 4: + IC(1.126 ns) + CELL(0.535 ns) = 7.227 ns; Loc. = LCCOMB_X17_Y6_N16; Fanout = 1; COMB Node = 'lcd:inst\|Equal0~148'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.661 ns" { lcd:inst|clkcnt[5] lcd:inst|Equal0~148 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.614 ns) 8.230 ns lcd:inst\|Equal0 5 COMB LCCOMB_X17_Y6_N4 17 " "Info: 5: + IC(0.389 ns) + CELL(0.614 ns) = 8.230 ns; Loc. = LCCOMB_X17_Y6_N4; Fanout = 17; COMB Node = 'lcd:inst\|Equal0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.003 ns" { lcd:inst|Equal0~148 lcd:inst|Equal0 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.328 ns) + CELL(0.970 ns) 9.528 ns lcd:inst\|clkdiv 6 REG LCFF_X17_Y6_N7 3 " "Info: 6: + IC(0.328 ns) + CELL(0.970 ns) = 9.528 ns; Loc. = LCFF_X17_Y6_N7; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.298 ns" { lcd:inst|Equal0 lcd:inst|clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.451 ns) + CELL(0.666 ns) 11.645 ns lcd:inst\|clk_int 7 REG LCFF_X12_Y6_N23 2 " "Info: 7: + IC(1.451 ns) + CELL(0.666 ns) = 11.645 ns; Loc. = LCFF_X12_Y6_N23; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.117 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.865 ns ( 50.36 % ) " "Info: Total cell delay = 5.865 ns ( 50.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.780 ns ( 49.64 % ) " "Info: Total interconnect delay = 5.780 ns ( 49.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.645 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[5] lcd:inst|Equal0~148 lcd:inst|Equal0 lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.645 ns" { clk {} clk~combout {} div16:inst1|count[3] {} lcd:inst|clkcnt[5] {} lcd:inst|Equal0~148 {} lcd:inst|Equal0 {} lcd:inst|clkdiv {} lcd:inst|clk_int {} } { 0.000ns 0.000ns 1.449ns 1.037ns 1.126ns 0.389ns 0.328ns 1.451ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.535ns 0.614ns 0.970ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.671 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 10.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd_test.bdf" "" { Schematic "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.449 ns) + CELL(0.970 ns) 3.559 ns div16:inst1\|count\[3\] 2 REG LCFF_X15_Y6_N9 17 " "Info: 2: + IC(1.449 ns) + CELL(0.970 ns) = 3.559 ns; Loc. = LCFF_X15_Y6_N9; Fanout = 17; REG Node = 'div16:inst1\|count\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.419 ns" { clk div16:inst1|count[3] } "NODE_NAME" } } { "DIV16.v" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/DIV16.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.970 ns) 5.566 ns lcd:inst\|clkcnt\[1\] 3 REG LCFF_X18_Y6_N3 3 " "Info: 3: + IC(1.037 ns) + CELL(0.970 ns) = 5.566 ns; Loc. = LCFF_X18_Y6_N3; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.007 ns" { div16:inst1|count[3] lcd:inst|clkcnt[1] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.748 ns) + CELL(0.202 ns) 6.516 ns lcd:inst\|Equal0~147 4 COMB LCCOMB_X17_Y6_N14 1 " "Info: 4: + IC(0.748 ns) + CELL(0.202 ns) = 6.516 ns; Loc. = LCCOMB_X17_Y6_N14; Fanout = 1; COMB Node = 'lcd:inst\|Equal0~147'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.950 ns" { lcd:inst|clkcnt[1] lcd:inst|Equal0~147 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.370 ns) 7.256 ns lcd:inst\|Equal0 5 COMB LCCOMB_X17_Y6_N4 17 " "Info: 5: + IC(0.370 ns) + CELL(0.370 ns) = 7.256 ns; Loc. = LCCOMB_X17_Y6_N4; Fanout = 17; COMB Node = 'lcd:inst\|Equal0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.740 ns" { lcd:inst|Equal0~147 lcd:inst|Equal0 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.328 ns) + CELL(0.970 ns) 8.554 ns lcd:inst\|clkdiv 6 REG LCFF_X17_Y6_N7 3 " "Info: 6: + IC(0.328 ns) + CELL(0.970 ns) = 8.554 ns; Loc. = LCFF_X17_Y6_N7; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.298 ns" { lcd:inst|Equal0 lcd:inst|clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.451 ns) + CELL(0.666 ns) 10.671 ns lcd:inst\|clk_int 7 REG LCFF_X12_Y6_N23 2 " "Info: 7: + IC(1.451 ns) + CELL(0.666 ns) = 10.671 ns; Loc. = LCFF_X12_Y6_N23; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.117 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.288 ns ( 49.55 % ) " "Info: Total cell delay = 5.288 ns ( 49.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.383 ns ( 50.45 % ) " "Info: Total interconnect delay = 5.383 ns ( 50.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.671 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[1] lcd:inst|Equal0~147 lcd:inst|Equal0 lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.671 ns" { clk {} clk~combout {} div16:inst1|count[3] {} lcd:inst|clkcnt[1] {} lcd:inst|Equal0~147 {} lcd:inst|Equal0 {} lcd:inst|clkdiv {} lcd:inst|clk_int {} } { 0.000ns 0.000ns 1.449ns 1.037ns 0.748ns 0.370ns 0.328ns 1.451ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.202ns 0.370ns 0.970ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.645 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[5] lcd:inst|Equal0~148 lcd:inst|Equal0 lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.645 ns" { clk {} clk~combout {} div16:inst1|count[3] {} lcd:inst|clkcnt[5] {} lcd:inst|Equal0~148 {} lcd:inst|Equal0 {} lcd:inst|clkdiv {} lcd:inst|clk_int {} } { 0.000ns 0.000ns 1.449ns 1.037ns 1.126ns 0.389ns 0.328ns 1.451ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.535ns 0.614ns 0.970ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.671 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[1] lcd:inst|Equal0~147 lcd:inst|Equal0 lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.671 ns" { clk {} clk~combout {} div16:inst1|count[3] {} lcd:inst|clkcnt[1] {} lcd:inst|Equal0~147 {} lcd:inst|Equal0 {} lcd:inst|clkdiv {} lcd:inst|clk_int {} } { 0.000ns 0.000ns 1.449ns 1.037ns 0.748ns 0.370ns 0.328ns 1.451ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.202ns 0.370ns 0.970ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns - Shortest register register " "Info: - Shortest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|clk_int 1 REG LCFF_X12_Y6_N23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y6_N23; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst|clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns lcd:inst\|clk_int~2 2 COMB LCCOMB_X12_Y6_N22 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X12_Y6_N22; Fanout = 1; COMB Node = 'lcd:inst\|clk_int~2'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { lcd:inst|clk_int lcd:inst|clk_int~2 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns lcd:inst\|clk_int 3 REG LCFF_X12_Y6_N23 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X12_Y6_N23; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { lcd:inst|clk_int~2 lcd:inst|clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { lcd:inst|clk_int lcd:inst|clk_int~2 lcd:inst|clk_int } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { lcd:inst|clk_int {} lcd:inst|clk_int~2 {} lcd:inst|clk_int {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.645 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[5] lcd:inst|Equal0~148 lcd:inst|Equal0 lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.645 ns" { clk {} clk~combout {} div16:inst1|count[3] {} lcd:inst|clkcnt[5] {} lcd:inst|Equal0~148 {} lcd:inst|Equal0 {} lcd:inst|clkdiv {} lcd:inst|clk_int {} } { 0.000ns 0.000ns 1.449ns 1.037ns 1.126ns 0.389ns 0.328ns 1.451ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.535ns 0.614ns 0.970ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.671 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[1] lcd:inst|Equal0~147 lcd:inst|Equal0 lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.671 ns" { clk {} clk~combout {} div16:inst1|count[3] {} lcd:inst|clkcnt[1] {} lcd:inst|Equal0~147 {} lcd:inst|Equal0 {} lcd:inst|clkdiv {} lcd:inst|clk_int {} } { 0.000ns 0.000ns 1.449ns 1.037ns 0.748ns 0.370ns 0.328ns 1.451ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.202ns 0.370ns 0.970ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { lcd:inst|clk_int lcd:inst|clk_int~2 lcd:inst|clk_int } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { lcd:inst|clk_int {} lcd:inst|clk_int~2 {} lcd:inst|clk_int {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}