prev_cmp_proj.tan.qmsg

基于QuartusII的LCD1602-Verilog 源代码

{ "Info" "ITDB_FULL_TCO_RESULT" "clk LCD_D\[5\] lcd:inst\|counter\[2\] 33.220 ns register " "Info: tco from clock \"clk\" to destination pin \"LCD_D\[5\]\" through register \"lcd:inst\|counter\[2\]\" is 33.220 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 15.004 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 15.004 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd_test.bdf" "" { Schematic "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(0.970 ns) 3.610 ns div16:inst1\|count\[3\] 2 REG LCFF_X22_Y10_N15 17 " "Info: 2: + IC(1.500 ns) + CELL(0.970 ns) = 3.610 ns; Loc. = LCFF_X22_Y10_N15; Fanout = 17; REG Node = 'div16:inst1\|count\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.470 ns" { clk div16:inst1|count[3] } "NODE_NAME" } } { "DIV16.v" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/DIV16.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.603 ns) + CELL(0.970 ns) 5.183 ns lcd:inst\|clkcnt\[4\] 3 REG LCFF_X21_Y10_N9 3 " "Info: 3: + IC(0.603 ns) + CELL(0.970 ns) = 5.183 ns; Loc. = LCFF_X21_Y10_N9; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { div16:inst1|count[3] lcd:inst|clkcnt[4] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.535 ns) 6.756 ns lcd:inst\|Equal0~148 4 COMB LCCOMB_X20_Y10_N22 1 " "Info: 4: + IC(1.038 ns) + CELL(0.535 ns) = 6.756 ns; Loc. = LCCOMB_X20_Y10_N22; Fanout = 1; COMB Node = 'lcd:inst\|Equal0~148'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { lcd:inst|clkcnt[4] lcd:inst|Equal0~148 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.357 ns) + CELL(0.589 ns) 7.702 ns lcd:inst\|Equal0 5 COMB LCCOMB_X20_Y10_N20 17 " "Info: 5: + IC(0.357 ns) + CELL(0.589 ns) = 7.702 ns; Loc. = LCCOMB_X20_Y10_N20; Fanout = 17; COMB Node = 'lcd:inst\|Equal0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.946 ns" { lcd:inst|Equal0~148 lcd:inst|Equal0 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.329 ns) + CELL(0.970 ns) 9.001 ns lcd:inst\|clkdiv 6 REG LCFF_X20_Y10_N17 3 " "Info: 6: + IC(0.329 ns) + CELL(0.970 ns) = 9.001 ns; Loc. = LCFF_X20_Y10_N17; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { lcd:inst|Equal0 lcd:inst|clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.423 ns) + CELL(0.970 ns) 11.394 ns lcd:inst\|clk_int 7 REG LCFF_X14_Y9_N19 2 " "Info: 7: + IC(1.423 ns) + CELL(0.970 ns) = 11.394 ns; Loc. = LCFF_X14_Y9_N19; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.105 ns) + CELL(0.000 ns) 13.499 ns lcd:inst\|clk_int~clkctrl 8 COMB CLKCTRL_G5 19 " "Info: 8: + IC(2.105 ns) + CELL(0.000 ns) = 13.499 ns; Loc. = CLKCTRL_G5; Fanout = 19; COMB Node = 'lcd:inst\|clk_int~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.105 ns" { lcd:inst|clk_int lcd:inst|clk_int~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 15.004 ns lcd:inst\|counter\[2\] 9 REG LCFF_X15_Y9_N19 11 " "Info: 9: + IC(0.839 ns) + CELL(0.666 ns) = 15.004 ns; Loc. = LCFF_X15_Y9_N19; Fanout = 11; REG Node = 'lcd:inst\|counter\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fl