📄 prev_cmp_proj.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "23 " "Warning: Found 23 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div16:inst1\|count\[3\] " "Info: Detected ripple clock \"div16:inst1\|count\[3\]\" as buffer" { } { { "DIV16.v" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/DIV16.v" 12 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "div16:inst1\|count\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[1\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[1\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[2\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[2\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[0\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[0\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[3\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[3\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[10\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[10\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[10\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[11\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[11\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[11\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[9\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[9\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[9\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[8\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[8\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[8\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[5\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[5\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[6\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[6\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[6\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[7\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[7\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[7\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[4\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[4\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[4\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[15\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[15\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[15\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[12\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[12\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[12\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[14\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[14\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[14\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[13\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[13\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[13\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|Equal0~147 " "Info: Detected gated clock \"lcd:inst\|Equal0~147\" as buffer" { } { { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|Equal0~147" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|Equal0~149 " "Info: Detected gated clock \"lcd:inst\|Equal0~149\" as buffer" { } { { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|Equal0~149" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|Equal0~148 " "Info: Detected gated clock \"lcd:inst\|Equal0~148\" as buffer" { } { { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|Equal0~148" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|Equal0~150 " "Info: Detected gated clock \"lcd:inst\|Equal0~150\" as buffer" { } { { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|Equal0~150" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkdiv " "Info: Detected ripple clock \"lcd:inst\|clkdiv\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkdiv" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clk_int " "Info: Detected ripple clock \"lcd:inst\|clk_int\" as buffer" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clk_int" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lcd:inst\|counter\[3\] register lcd:inst\|counter\[6\] 198.33 MHz 5.042 ns Internal " "Info: Clock \"clk\" has Internal fmax of 198.33 MHz between source register \"lcd:inst\|counter\[3\]\" and destination register \"lcd:inst\|counter\[6\]\" (period= 5.042 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.761 ns + Longest register register " "Info: + Longest register to register delay is 3.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|counter\[3\] 1 REG LCFF_X15_Y9_N21 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y9_N21; Fanout = 13; REG Node = 'lcd:inst\|counter\[3\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst|counter[3] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.496 ns) + CELL(0.534 ns) 1.030 ns lcd:inst\|Equal11~39 2 COMB LCCOMB_X15_Y9_N2 2 " "Info: 2: + IC(0.496 ns) + CELL(0.534 ns) = 1.030 ns; Loc. = LCCOMB_X15_Y9_N2; Fanout = 2; COMB Node = 'lcd:inst\|Equal11~39'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.030 ns" { lcd:inst|counter[3] lcd:inst|Equal11~39 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 136 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.382 ns) + CELL(0.206 ns) 1.618 ns lcd:inst\|LessThan6~82 3 COMB LCCOMB_X15_Y9_N8 4 " "Info: 3: + IC(0.382 ns) + CELL(0.206 ns) = 1.618 ns; Loc. = LCCOMB_X15_Y9_N8; Fanout = 4; COMB Node = 'lcd:inst\|LessThan6~82'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.588 ns" { lcd:inst|Equal11~39 lcd:inst|LessThan6~82 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 194 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.706 ns) 2.717 ns lcd:inst\|counter\[0\]~435 4 COMB LCCOMB_X15_Y9_N14 2 " "Info: 4: + IC(0.393 ns) + CELL(0.706 ns) = 2.717 ns; Loc. = LCCOMB_X15_Y9_N14; Fanout = 2; COMB Node = 'lcd:inst\|counter\[0\]~435'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.099 ns" { lcd:inst|LessThan6~82 lcd:inst|counter[0]~435 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.803 ns lcd:inst\|counter\[1\]~437 5 COMB LCCOMB_X15_Y9_N16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 2.803 ns; Loc. = LCCOMB_X15_Y9_N16; Fanout = 2; COMB Node = 'lcd:inst\|counter\[1\]~437'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lcd:inst|counter[0]~435 lcd:inst|counter[1]~437 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.889 ns lcd:inst\|counter\[2\]~439 6 COMB LCCOMB_X15_Y9_N18 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 2.889 ns; Loc. = LCCOMB_X15_Y9_N18; Fanout = 2; COMB Node = 'lcd:inst\|counter\[2\]~439'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lcd:inst|counter[1]~437 lcd:inst|counter[2]~439 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.975 ns lcd:inst\|counter\[3\]~441 7 COMB LCCOMB_X15_Y9_N20 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 2.975 ns; Loc. = LCCOMB_X15_Y9_N20; Fanout = 2; COMB Node = 'lcd:inst\|counter\[3\]~441'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lcd:inst|counter[2]~439 lcd:inst|counter[3]~441 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.061 ns lcd:inst\|counter\[4\]~444 8 COMB LCCOMB_X15_Y9_N22 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 3.061 ns; Loc. = LCCOMB_X15_Y9_N22; Fanout = 2; COMB Node = 'lcd:inst\|counter\[4\]~444'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lcd:inst|counter[3]~441 lcd:inst|counter[4]~444 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.147 ns lcd:inst\|counter\[5\]~446 9 COMB LCCOMB_X15_Y9_N24 1 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 3.147 ns; Loc. = LCCOMB_X15_Y9_N24; Fanout = 1; COMB Node = 'lcd:inst\|counter\[5\]~446'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lcd:inst|counter[4]~444 lcd:inst|counter[5]~446 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 3.653 ns lcd:inst\|counter\[6\]~447 10 COMB LCCOMB_X15_Y9_N26 1 " "Info: 10: + IC(0.000 ns) + CELL(0.506 ns) = 3.653 ns; Loc. = LCCOMB_X15_Y9_N26; Fanout = 1; COMB Node = 'lcd:inst\|counter\[6\]~447'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { lcd:inst|counter[5]~446 lcd:inst|counter[6]~447 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.761 ns lcd:inst\|counter\[6\] 11 REG LCFF_X15_Y9_N27 7 " "Info: 11: + IC(0.000 ns) + CELL(0.108 ns) = 3.761 ns; Loc. = LCFF_X15_Y9_N27; Fanout = 7; REG Node = 'lcd:inst\|counter\[6\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { lcd:inst|counter[6]~447 lcd:inst|counter[6] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.490 ns ( 66.21 % ) " "Info: Total cell delay = 2.490 ns ( 66.21 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.271 ns ( 33.79 % ) " "Info: Total interconnect delay = 1.271 ns ( 33.79 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.761 ns" { lcd:inst|counter[3] lcd:inst|Equal11~39 lcd:inst|LessThan6~82 lcd:inst|counter[0]~435 lcd:inst|counter[1]~437 lcd:inst|counter[2]~439 lcd:inst|counter[3]~441 lcd:inst|counter[4]~444 lcd:inst|counter[5]~446 lcd:inst|counter[6]~447 lcd:inst|counter[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.761 ns" { lcd:inst|counter[3] {} lcd:inst|Equal11~39 {} lcd:inst|LessThan6~82 {} lcd:inst|counter[0]~435 {} lcd:inst|counter[1]~437 {} lcd:inst|counter[2]~439 {} lcd:inst|counter[3]~441 {} lcd:inst|counter[4]~444 {} lcd:inst|counter[5]~446 {} lcd:inst|counter[6]~447 {} lcd:inst|counter[6] {} } { 0.000ns 0.496ns 0.382ns 0.393ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.534ns 0.206ns 0.706ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.017 ns - Smallest " "Info: - Smallest clock skew is -1.017 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.987 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 13.987 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd_test.bdf" "" { Schematic "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(0.970 ns) 3.610 ns div16:inst1\|count\[3\] 2 REG LCFF_X22_Y10_N15 17 " "Info: 2: + IC(1.500 ns) + CELL(0.970 ns) = 3.610 ns; Loc. = LCFF_X22_Y10_N15; Fanout = 17; REG Node = 'div16:inst1\|count\[3\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.470 ns" { clk div16:inst1|count[3] } "NODE_NAME" } } { "DIV16.v" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/DIV16.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.603 ns) + CELL(0.970 ns) 5.183 ns lcd:inst\|clkcnt\[1\] 3 REG LCFF_X21_Y10_N3 3 " "Info: 3: + IC(0.603 ns) + CELL(0.970 ns) = 5.183 ns; Loc. = LCFF_X21_Y10_N3; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[1\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { div16:inst1|count[3] lcd:inst|clkcnt[1] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.737 ns) + CELL(0.202 ns) 6.122 ns lcd:inst\|Equal0~147 4 COMB LCCOMB_X20_Y10_N0 1 " "Info: 4: + IC(0.737 ns) + CELL(0.202 ns) = 6.122 ns; Loc. = LCCOMB_X20_Y10_N0; Fanout = 1; COMB Node = 'lcd:inst\|Equal0~147'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.939 ns" { lcd:inst|clkcnt[1] lcd:inst|Equal0~147 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.357 ns) + CELL(0.206 ns) 6.685 ns lcd:inst\|Equal0 5 COMB LCCOMB_X20_Y10_N20 17 " "Info: 5: + IC(0.357 ns) + CELL(0.206 ns) = 6.685 ns; Loc. = LCCOMB_X20_Y10_N20; Fanout = 17; COMB Node = 'lcd:inst\|Equal0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.563 ns" { lcd:inst|Equal0~147 lcd:inst|Equal0 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.329 ns) + CELL(0.970 ns) 7.984 ns lcd:inst\|clkdiv 6 REG LCFF_X20_Y10_N17 3 " "Info: 6: + IC(0.329 ns) + CELL(0.970 ns) = 7.984 ns; Loc. = LCFF_X20_Y10_N17; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { lcd:inst|Equal0 lcd:inst|clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.423 ns) + CELL(0.970 ns) 10.377 ns lcd:inst\|clk_int 7 REG LCFF_X14_Y9_N19 2 " "Info: 7: + IC(1.423 ns) + CELL(0.970 ns) = 10.377 ns; Loc. = LCFF_X14_Y9_N19; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.105 ns) + CELL(0.000 ns) 12.482 ns lcd:inst\|clk_int~clkctrl 8 COMB CLKCTRL_G5 19 " "Info: 8: + IC(2.105 ns) + CELL(0.000 ns) = 12.482 ns; Loc. = CLKCTRL_G5; Fanout = 19; COMB Node = 'lcd:inst\|clk_int~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.105 ns" { lcd:inst|clk_int lcd:inst|clk_int~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 13.987 ns lcd:inst\|counter\[6\] 9 REG LCFF_X15_Y9_N27 7 " "Info: 9: + IC(0.839 ns) + CELL(0.666 ns) = 13.987 ns; Loc. = LCFF_X15_Y9_N27; Fanout = 7; REG Node = 'lcd:inst\|counter\[6\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { lcd:inst|clk_int~clkctrl lcd:inst|counter[6] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.094 ns ( 43.57 % ) " "Info: Total cell delay = 6.094 ns ( 43.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.893 ns ( 56.43 % ) " "Info: Total interconnect delay = 7.893 ns ( 56.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.987 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[1] lcd:inst|Equal0~147 lcd:inst|Equal0 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|counter[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.987 ns" { clk {} clk~combout {} div16:inst1|count[3] {} lcd:inst|clkcnt[1] {} lcd:inst|Equal0~147 {} lcd:inst|Equal0 {} lcd:inst|clkdiv {} lcd:inst|clk_int {} lcd:inst|clk_int~clkctrl {} lcd:inst|counter[6] {} } { 0.000ns 0.000ns 1.500ns 0.603ns 0.737ns 0.357ns 0.329ns 1.423ns 2.105ns 0.839ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.202ns 0.206ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 15.004 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 15.004 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd_test.bdf" "" { Schematic "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(0.970 ns) 3.610 ns div16:inst1\|count\[3\] 2 REG LCFF_X22_Y10_N15 17 " "Info: 2: + IC(1.500 ns) + CELL(0.970 ns) = 3.610 ns; Loc. = LCFF_X22_Y10_N15; Fanout = 17; REG Node = 'div16:inst1\|count\[3\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.470 ns" { clk div16:inst1|count[3] } "NODE_NAME" } } { "DIV16.v" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/DIV16.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.603 ns) + CELL(0.970 ns) 5.183 ns lcd:inst\|clkcnt\[4\] 3 REG LCFF_X21_Y10_N9 3 " "Info: 3: + IC(0.603 ns) + CELL(0.970 ns) = 5.183 ns; Loc. = LCFF_X21_Y10_N9; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[4\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { div16:inst1|count[3] lcd:inst|clkcnt[4] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.535 ns) 6.756 ns lcd:inst\|Equal0~148 4 COMB LCCOMB_X20_Y10_N22 1 " "Info: 4: + IC(1.038 ns) + CELL(0.535 ns) = 6.756 ns; Loc. = LCCOMB_X20_Y10_N22; Fanout = 1; COMB Node = 'lcd:inst\|Equal0~148'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { lcd:inst|clkcnt[4] lcd:inst|Equal0~148 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.357 ns) + CELL(0.589 ns) 7.702 ns lcd:inst\|Equal0 5 COMB LCCOMB_X20_Y10_N20 17 " "Info: 5: + IC(0.357 ns) + CELL(0.589 ns) = 7.702 ns; Loc. = LCCOMB_X20_Y10_N20; Fanout = 17; COMB Node = 'lcd:inst\|Equal0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.946 ns" { lcd:inst|Equal0~148 lcd:inst|Equal0 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.329 ns) + CELL(0.970 ns) 9.001 ns lcd:inst\|clkdiv 6 REG LCFF_X20_Y10_N17 3 " "Info: 6: + IC(0.329 ns) + CELL(0.970 ns) = 9.001 ns; Loc. = LCFF_X20_Y10_N17; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { lcd:inst|Equal0 lcd:inst|clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.423 ns) + CELL(0.970 ns) 11.394 ns lcd:inst\|clk_int 7 REG LCFF_X14_Y9_N19 2 " "Info: 7: + IC(1.423 ns) + CELL(0.970 ns) = 11.394 ns; Loc. = LCFF_X14_Y9_N19; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.105 ns) + CELL(0.000 ns) 13.499 ns lcd:inst\|clk_int~clkctrl 8 COMB CLKCTRL_G5 19 " "Info: 8: + IC(2.105 ns) + CELL(0.000 ns) = 13.499 ns; Loc. = CLKCTRL_G5; Fanout = 19; COMB Node = 'lcd:inst\|clk_int~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.105 ns" { lcd:inst|clk_int lcd:inst|clk_int~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 15.004 ns lcd:inst\|counter\[3\] 9 REG LCFF_X15_Y9_N21 13 " "Info: 9: + IC(0.839 ns) + CELL(0.666 ns) = 15.004 ns; Loc. = LCFF_X15_Y9_N21; Fanout = 13; REG Node = 'lcd:inst\|counter\[3\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { lcd:inst|clk_int~clkctrl lcd:inst|counter[3] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.810 ns ( 45.39 % ) " "Info: Total cell delay = 6.810 ns ( 45.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.194 ns ( 54.61 % ) " "Info: Total interconnect delay = 8.194 ns ( 54.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.004 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[4] lcd:inst|Equal0~148 lcd:inst|Equal0 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|counter[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.004 ns" { clk {} clk~combout {} div16:inst1|count[3] {} lcd:inst|clkcnt[4] {} lcd:inst|Equal0~148 {} lcd:inst|Equal0 {} lcd:inst|clkdiv {} lcd:inst|clk_int {} lcd:inst|clk_int~clkctrl {} lcd:inst|counter[3] {} } { 0.000ns 0.000ns 1.500ns 0.603ns 1.038ns 0.357ns 0.329ns 1.423ns 2.105ns 0.839ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.535ns 0.589ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.987 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[1] lcd:inst|Equal0~147 lcd:inst|Equal0 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|counter[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.987 ns" { clk {} clk~combout {} div16:inst1|count[3] {} lcd:inst|clkcnt[1] {} lcd:inst|Equal0~147 {} lcd:inst|Equal0 {} lcd:inst|clkdiv {} lcd:inst|clk_int {} lcd:inst|clk_int~clkctrl {} lcd:inst|counter[6] {} } { 0.000ns 0.000ns 1.500ns 0.603ns 0.737ns 0.357ns 0.329ns 1.423ns 2.105ns 0.839ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.202ns 0.206ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.004 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[4] lcd:inst|Equal0~148 lcd:inst|Equal0 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|counter[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.004 ns" { clk {} clk~combout {} div16:inst1|count[3] {} lcd:inst|clkcnt[4] {} lcd:inst|Equal0~148 {} lcd:inst|Equal0 {} lcd:inst|clkdiv {} lcd:inst|clk_int {} lcd:inst|clk_int~clkctrl {} lcd:inst|counter[3] {} } { 0.000ns 0.000ns 1.500ns 0.603ns 1.038ns 0.357ns 0.329ns 1.423ns 2.105ns 0.839ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.535ns 0.589ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.761 ns" { lcd:inst|counter[3] lcd:inst|Equal11~39 lcd:inst|LessThan6~82 lcd:inst|counter[0]~435 lcd:inst|counter[1]~437 lcd:inst|counter[2]~439 lcd:inst|counter[3]~441 lcd:inst|counter[4]~444 lcd:inst|counter[5]~446 lcd:inst|counter[6]~447 lcd:inst|counter[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.761 ns" { lcd:inst|counter[3] {} lcd:inst|Equal11~39 {} lcd:inst|LessThan6~82 {} lcd:inst|counter[0]~435 {} lcd:inst|counter[1]~437 {} lcd:inst|counter[2]~439 {} lcd:inst|counter[3]~441 {} lcd:inst|counter[4]~444 {} lcd:inst|counter[5]~446 {} lcd:inst|counter[6]~447 {} lcd:inst|counter[6] {} } { 0.000ns 0.496ns 0.382ns 0.393ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.534ns 0.206ns 0.706ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.987 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[1] lcd:inst|Equal0~147 lcd:inst|Equal0 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|counter[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.987 ns" { clk {} clk~combout {} div16:inst1|count[3] {} lcd:inst|clkcnt[1] {} lcd:inst|Equal0~147 {} lcd:inst|Equal0 {} lcd:inst|clkdiv {} lcd:inst|clk_int {} lcd:inst|clk_int~clkctrl {} lcd:inst|counter[6] {} } { 0.000ns 0.000ns 1.500ns 0.603ns 0.737ns 0.357ns 0.329ns 1.423ns 2.105ns 0.839ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.202ns 0.206ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.004 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[4] lcd:inst|Equal0~148 lcd:inst|Equal0 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|counter[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.004 ns" { clk {} clk~combout {} div16:inst1|count[3] {} lcd:inst|clkcnt[4] {} lcd:inst|Equal0~148 {} lcd:inst|Equal0 {} lcd:inst|clkdiv {} lcd:inst|clk_int {} lcd:inst|clk_int~clkctrl {} lcd:inst|counter[3] {} } { 0.000ns 0.000ns 1.500ns 0.603ns 1.038ns 0.357ns 0.329ns 1.423ns 2.105ns 0.839ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.535ns 0.589ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -