proj.map.qmsg

基于QuartusII的LCD1602-Verilog 源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 17 09:37:15 2008 " "Info: Processing started: Wed Dec 17 09:37:15 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LCD_Test -c Proj " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LCD_Test -c Proj" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "char_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file char_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 char_ram-fun " "Info: Found design unit 1: char_ram-fun" {  } { { "char_ram.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/char_ram.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 char_ram " "Info: Found entity 1: char_ram" {  } { { "char_ram.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/char_ram.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DIV16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DIV16.v" { { "Info" "ISGN_ENTITY_NAME" "1 div16 " "Info: Found entity 1: div16" {  } { { "DIV16.v" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/DIV16.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lcd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcd-Behavioral " "Info: Found design unit 1: lcd-Behavioral" {  } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lcd " "Info: Found entity 1: lcd" {  } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_test " "Info: Found entity 1: lcd_test" {  } { { "lcd_test.bdf" "" { Schematic "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd_test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd_test " "Info: Elaborating entity \"lcd_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "lcd_test " "Warning: Processing legacy GDF or BDF entity \"lcd_test\" with Max+Plus II bus and instance naming rules" {  } { { "lcd_test.bdf" "" { Schematic "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd_test.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd lcd:inst " "Info: Elaborating entity \"lcd\" for hierarchy \"lcd:inst\"" {  } { { "lcd_test.bdf" "inst" { Schematic "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd_test.bdf" { { 200 528 680 328 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "char_ram lcd:inst\|char_ram:aa " "Info: Elaborating entity \"char_ram\" for hierarchy \"lcd:inst\|char_ram:aa\"" {  } { { "lcd.vhd" "aa" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 122 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div16 div16:inst1 " "Info: Elaborating entity \"div16\" for hierarchy \"div16:inst1\"" {  } { { "lcd_test.bdf" "inst1" { Schematic "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd_test.bdf" { { 64 488 584 160 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 DIV16.v(12) " "Warning (10230): Verilog HDL assignment warning at DIV16.v(12): truncated value with size 32 to match size of target (4)" {  } { { "DIV16.v" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/DIV16.v" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lcd:inst\|state\[10\] data_in GND " "Warning (14130): Reduced register \"lcd:inst\|state\[10\]\" with stuck data_in port to stuck value GND" {  } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lcd:inst\|state\[8\] data_in GND " "Warning (14130): Reduced register \"lcd:inst\|state\[8\]\" with stuck data_in port to stuck value GND" {  } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lcd:inst\|state\[6\] data_in GND " "Warning (14130): Reduced register \"lcd:inst\|state\[6\]\" with stuck data_in port to stuck value GND" {  } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lcd:inst\|state\[1\] data_in GND " "Warning (14130): Reduced register \"lcd:inst\|state\[1\]\" with stuck data_in port to stuck value GND" {  } { { "lcd.vhd" "" { Text "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd" 150 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "led GND " "Warning (13410): Pin \"led\" stuck at GND" {  } { { "lcd_test.bdf" "" { Schematic "E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd_test.bdf" { { 360 432 608 376 "led" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "159 " "Info: Implemented 159 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "145 " "Info: Implemented 145 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "161 " "Info: Allocated 161 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 17 09:37:20 2008 " "Info: Processing ended: Wed Dec 17 09:37:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}