proj.qsf

基于QuartusII的LCD1602-Verilog 源代码

# Copyright (C) 1991-2005 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		Proj_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.2 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:01:08  APRIL 18, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_23 -to clk
set_location_assignment PIN_67 -to LCD_D[0]
set_location_assignment PIN_63 -to LCD_D[1]
set_location_assignment PIN_60 -to LCD_D[2]
set_location_assignment PIN_58 -to LCD_D[3]
set_location_assignment PIN_56 -to LCD_D[4]
set_location_assignment PIN_57 -to LCD_D[5]
set_location_assignment PIN_59 -to LCD_D[6]
set_location_assignment PIN_61 -to LCD_D[7]
set_location_assignment PIN_69 -to LCD_E
set_location_assignment PIN_75 -to LCD_RS
set_location_assignment PIN_72 -to LCD_RW
set_location_assignment PIN_142 -to SYS_RST

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY lcd_test
set_global_assignment -name USER_LIBRARIES "f:\\i2c_altera/"

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP2C5Q208C8
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

# Assembler Assignments
# =====================
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1

set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name VHDL_FILE char_ram.vhd
set_global_assignment -name VERILOG_FILE DIV16.v
set_global_assignment -name VHDL_FILE lcd.vhd
set_global_assignment -name BDF_FILE lcd_test.bdf
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_location_assignment PIN_88 -to led