proj.tan.summary

基于QuartusII的LCD1602-Verilog 源代码

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 33.587 ns
From           : lcd:inst|counter[3]
To             : LCD_D[5]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 198.93 MHz ( period = 5.027 ns )
From           : lcd:inst|counter[3]
To             : lcd:inst|counter[6]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : lcd:inst|clk_int
To             : lcd:inst|clk_int
From Clock     : clk
To Clock       : clk
Failed Paths   : 14

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 14

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