proj.map.rpt

基于QuartusII的LCD1602-Verilog 源代码

+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+
; char_ram.vhd                     ; yes             ; User VHDL File                     ; E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/char_ram.vhd ;
; DIV16.v                          ; yes             ; User Verilog HDL File              ; E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/DIV16.v      ;
; lcd.vhd                          ; yes             ; User VHDL File                     ; E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd.vhd      ;
; lcd_test.bdf                     ; yes             ; User Block Diagram/Schematic File  ; E:/logic/Verilog/QuickSOPC-1C6/ep2c5/lcd1602/lcd_test.bdf ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Estimated Total logic elements              ; 141     ;
;                                             ;         ;
; Total combinational functions               ; 141     ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 78      ;
;     -- 3 input functions                    ; 15      ;
;     -- <=2 input functions                  ; 48      ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 110     ;
;     -- arithmetic mode                      ; 31      ;
;                                             ;         ;
; Total registers                             ; 42      ;
;     -- Dedicated logic registers            ; 42      ;
;     -- I/O registers                        ; 0       ;
;                                             ;         ;
; I/O pins                                    ; 14      ;
; Maximum fan-out node                        ; SYS_RST ;
; Maximum fan-out                             ; 42      ;
; Total fan-out                               ; 624     ;
; Average fan-out                             ; 3.17    ;
+---------------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                    ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name            ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+
; |lcd_test                  ; 141 (0)           ; 42 (0)       ; 0           ; 0            ; 0       ; 0         ; 14   ; 0            ; |lcd_test                      ; work         ;
;    |div16:inst1|           ; 4 (4)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lcd_test|div16:inst1          ; work         ;
;    |lcd:inst|              ; 137 (127)         ; 38 (38)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lcd_test|lcd:inst             ; work         ;
;       |char_ram:aa|        ; 10 (10)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lcd_test|lcd:inst|char_ram:aa ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; lcd:inst|state[1,6,8,10]              ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 4 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 42    ;
; Number of registers using Synchronous Clear  ; 23    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 42    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 12    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |lcd_test|lcd:inst|div_counter[0] ;
; 4:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |lcd_test|lcd:inst|counter[5]     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |lcd_test|lcd:inst|char_addr[4]   ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |lcd_test|lcd:inst|char_addr[0]   ;
; 6:1                ; 6 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; No         ; |lcd_test|lcd:inst|data[1]~46     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Wed Dec 17 09:37:15 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LCD_Test -c Proj
Info: Found 2 design units, including 1 entities, in source file char_ram.vhd
    Info: Found design unit 1: char_ram-fun
    Info: Found entity 1: char_ram
Info: Found 1 design units, including 1 entities, in source file DIV16.v
    Info: Found entity 1: div16
Info: Found 2 design units, including 1 entities, in source file lcd.vhd
    Info: Found design unit 1: lcd-Behavioral
    Info: Found entity 1: lcd
Info: Found 1 design units, including 1 entities, in source file lcd_test.bdf
    Info: Found entity 1: lcd_test
Info: Elaborating entity "lcd_test" for the top level hierarchy
Warning: Processing legacy GDF or BDF entity "lcd_test" with Max+Plus II bus and instance naming rules
Info: Elaborating entity "lcd" for hierarchy "lcd:inst"
Info: Elaborating entity "char_ram" for hierarchy "lcd:inst|char_ram:aa"
Info: Elaborating entity "div16" for hierarchy "div16:inst1"
Warning (10230): Verilog HDL assignment warning at DIV16.v(12): truncated value with size 32 to match size of target (4)
Warning (14130): Reduced register "lcd:inst|state[10]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "lcd:inst|state[8]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "lcd:inst|state[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "lcd:inst|state[1]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "led" stuck at GND
Info: Implemented 159 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 12 output pins
    Info: Implemented 145 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Allocated 161 megabytes of memory during processing
    Info: Processing ended: Wed Dec 17 09:37:20 2008
    Info: Elapsed time: 00:00:05