📄 usbd_udphs.lst
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885 //------------------------------------------------------------------------------
886 // Configure an endpoint with the provided endpoint descriptor
887 // pDdescriptor Pointer to the endpoint descriptor
888 //
889 //------------------------------------------------------------------------------
890 void USBD_ConfigureEndpoint(const USBEndpointDescriptor *pDescriptor)
891 {
892 Endpoint *pEndpoint;
893 unsigned char bEndpoint;
894 unsigned char bType;
895 unsigned char bEndpointDir;
896 unsigned char bSizeEpt = 0;
897
898 // NULL descriptor -> Control endpoint 0
899 if (pDescriptor == 0) {
900
901 bEndpoint = 0;
902 pEndpoint = &(endpoints[bEndpoint]);
903 bType = USBEndpointDescriptor_CONTROL;
904 bEndpointDir = 0;
905 pEndpoint->size = BOARD_USB_ENDPOINTS_MAXPACKETSIZE(0);
906 pEndpoint->bank = BOARD_USB_ENDPOINTS_BANKS(0);
907 }
908 else {
909
910 // The endpoint number
911 bEndpoint = USBEndpointDescriptor_GetNumber(pDescriptor);
912 pEndpoint = &(endpoints[bEndpoint]);
913 // Transfer type: Control, Isochronous, Bulk, Interrupt
914 bType = USBEndpointDescriptor_GetType(pDescriptor);
915 // Direction, ignored for control endpoints
916 bEndpointDir = USBEndpointDescriptor_GetDirection(pDescriptor);
917 pEndpoint->size = USBEndpointDescriptor_GetMaxPacketSize(pDescriptor);
918 pEndpoint->bank = BOARD_USB_ENDPOINTS_BANKS(bEndpoint);
919 }
920
921 // Abort the current transfer is the endpoint was configured and in
922 // Write or Read state
923 if( (pEndpoint->state == UDP_ENDPOINT_RECEIVING)
924 || (pEndpoint->state == UDP_ENDPOINT_SENDING) ) {
925
926 UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_RESET);
927 }
928 pEndpoint->state = UDP_ENDPOINT_IDLE;
929
930 // Disable endpoint
931 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLDIS = AT91C_UDPHS_SHRT_PCKT
932 | AT91C_UDPHS_BUSY_BANK
933 | AT91C_UDPHS_NAK_OUT
934 | AT91C_UDPHS_NAK_IN
935 | AT91C_UDPHS_STALL_SNT
936 | AT91C_UDPHS_RX_SETUP
937 | AT91C_UDPHS_TX_PK_RDY
938 | AT91C_UDPHS_TX_COMPLT
939 | AT91C_UDPHS_RX_BK_RDY
940 | AT91C_UDPHS_ERR_OVFLW
941 | AT91C_UDPHS_MDATA_RX
942 | AT91C_UDPHS_DATAX_RX
943 | AT91C_UDPHS_NYET_DIS
944 | AT91C_UDPHS_INTDIS_DMA
945 | AT91C_UDPHS_AUTO_VALID
946 | AT91C_UDPHS_EPT_DISABL;
947
948 // Reset Endpoint Fifos
949 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCLRSTA = AT91C_UDPHS_TOGGLESQ | AT91C_UDPHS_FRCESTALL;
950 AT91C_BASE_UDPHS->UDPHS_EPTRST = 1<<bEndpoint;
951
952 // Configure endpoint
953 if( pEndpoint->size == 8 ) {
954 bSizeEpt = 0;
955 }
956 else if ( pEndpoint->size == 16 ) {
957 bSizeEpt = 1;
958 }
959 else if ( pEndpoint->size == 32 ) {
960 bSizeEpt = 2;
961 }
962 else if ( pEndpoint->size == 64 ) {
963 bSizeEpt = 3;
964 }
965 else if ( pEndpoint->size == 128 ) {
966 bSizeEpt = 4;
967 }
968 else if ( pEndpoint->size == 256 ) {
969 bSizeEpt = 5;
970 }
971 else if ( pEndpoint->size == 512 ) {
972 bSizeEpt = 6;
973 }
974 else if ( pEndpoint->size == 1024 ) {
975 bSizeEpt = 7;
976 } //else {
977 // sizeEpt = 0; // control endpoint
978 //}
979
980 // Configure endpoint
981 if (bType == USBEndpointDescriptor_CONTROL) {
982
983 // Enable endpoint IT for control endpoint
984 AT91C_BASE_UDPHS->UDPHS_IEN |= (1<<SHIFT_INTERUPT<<bEndpoint);
985 }
986
987
988 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG = bSizeEpt
989 | (bEndpointDir << 3)
990 | (bType << 4)
991 | ((pEndpoint->bank) << 6);
992
993 while( (signed int)AT91C_UDPHS_EPT_MAPD != (signed int)((AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG) & AT91C_UDPHS_EPT_MAPD) ) {
994
995 // resolved by clearing the reset IT in good place
996 trace_LOG(trace_ERROR, "PB bEndpoint: 0x%X\n\r", bEndpoint);
997 trace_LOG(trace_ERROR, "PB bSizeEpt: 0x%X\n\r", bSizeEpt);
998 trace_LOG(trace_ERROR, "PB bEndpointDir: 0x%X\n\r", bEndpointDir);
999 trace_LOG(trace_ERROR, "PB bType: 0x%X\n\r", bType);
1000 trace_LOG(trace_ERROR, "PB pEndpoint->bank: 0x%X\n\r", pEndpoint->bank);
1001 trace_LOG(trace_ERROR, "PB UDPHS_EPTCFG: 0x%X\n\r", AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG);
1002 for(;;);
1003 }
1004
1005 if (bType == USBEndpointDescriptor_CONTROL) {
1006
1007 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_RX_BK_RDY
1008 | AT91C_UDPHS_RX_SETUP
1009 | AT91C_UDPHS_EPT_ENABL;
1010 }
1011 else {
1012 #ifndef DMA
1013 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_EPT_ENABL;
1014 #else
1015 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_AUTO_VALID
1016 | AT91C_UDPHS_EPT_ENABL;
1017 #endif
1018 }
1019
1020 }
1021
1022 //------------------------------------------------------------------------------
1023 // Sends data through an USB endpoint (IN)
1024 // Sets up the transfer descriptor, write one or two data payloads
1025 // (depending on the number of FIFO banks for the endpoint) and then
1026 // starts the actual transfer. The operation is complete when all
1027 // the data has been sent.
1028 //------------------------------------------------------------------------------
1029 char USBD_Write( unsigned char bEndpoint,
1030 const void *pData,
1031 unsigned int dLength,
1032 TransferCallback fCallback,
1033 void *pArgument )
1034 {
1035 Endpoint *pEndpoint = &(endpoints[bEndpoint]);
1036 Transfer *pTransfer = &(pEndpoint->transfer);
1037
1038 // Return if the endpoint is not in IDLE state
1039 if (pEndpoint->state != UDP_ENDPOINT_IDLE) {
1040
1041 return USBD_STATUS_LOCKED;
1042 }
1043
1044 trace_LOG(trace_DEBUG, "Write%d(%d) ", bEndpoint, dLength);
1045
1046 // Setup the transfer descriptor
1047 pTransfer->pData = (void *) pData;
1048 pTransfer->remaining = dLength;
1049 pTransfer->buffered = 0;
1050 pTransfer->transferred = 0;
1051 pTransfer->fCallback = fCallback;
1052 pTransfer->pArgument = pArgument;
1053
1054 // Send one packet
1055 pEndpoint->state = UDP_ENDPOINT_SENDING;
1056
1057 #ifdef DMA
1058 // Test if endpoint type control
1059 if(AT91C_UDPHS_EPT_TYPE_CTL_EPT == (AT91C_UDPHS_EPT_TYPE&(AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG))) {
1060 #endif
1061 // Send the first packet
1062 UDPHS_WritePayload(bEndpoint);
1063 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTSETSTA = AT91C_UDPHS_TX_PK_RDY;
1064
1065 // If double buffering is enabled and there is data remaining,
1066 // prepare another packet
1067 if( (BOARD_USB_ENDPOINTS_BANKS(bEndpoint) > 1) && (pTransfer->remaining > 0) ) {
1068
1069 UDPHS_WritePayload( bEndpoint );
1070 }
1071 // Enable endpoint IT
1072 AT91C_BASE_UDPHS->UDPHS_IEN |= (1 << SHIFT_INTERUPT << bEndpoint);
1073 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_TX_PK_RDY;
1074
1075 #ifdef DMA
1076 }
1077 else {
1078
1079 // Others endpoints (not control)
1080 if( pTransfer->remaining > DMA_MAX_FIFO_SIZE ) {
1081
1082 // Transfer the max
1083 pTransfer->buffered = DMA_MAX_FIFO_SIZE;
1084 }
1085 else {
1086 // Transfer the good size
1087 pTransfer->buffered = pTransfer->remaining;
1088 }
1089
1090 trace_LOG(trace_DEBUG, "\n\r_WR:%d ", pTransfer->remaining );
1091 trace_LOG(trace_DEBUG, "B:%d ", pTransfer->buffered );
1092 trace_LOG(trace_DEBUG, "T:%d ", pTransfer->transferred );
1093
1094 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMAADDRESS = (unsigned int)(pTransfer->pData);
1095
1096 // Clear unwanted interrupts
1097 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMASTATUS;
1098 // Enable DMA endpoint interrupt
1099 AT91C_BASE_UDPHS->UDPHS_IEN |= (1 << SHIFT_DMA << bEndpoint);
1100 // DMA config
1101 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = 0; // raz
1102 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL =
1103 ( ((pTransfer->buffered << 16) & AT91C_UDPHS_BUFF_COUNT)
1104 | AT91C_UDPHS_END_B_EN
1105 | AT91C_UDPHS_END_BUFFIT
1106 | AT91C_UDPHS_CHANN_ENB );
1107 }
1108 #endif
1109
1110 return USBD_STATUS_SUCCESS;
1111 }
1112
1113 //------------------------------------------------------------------------------
1114 // Reads incoming data on an USB endpoint (OUT)
1115
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