📄 usbd_udphs.lst
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417
418 trace_LOG(trace_DEBUG, "E%d ", bEndpoint);
419
420 // Handle interrupts
421 // IN packet sent
422 if( (AT91C_UDPHS_TX_PK_RDY == (AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTL & AT91C_UDPHS_TX_PK_RDY))
423 && (0 == (status & AT91C_UDPHS_TX_PK_RDY )) ) {
424
425 trace_LOG(trace_DEBUG, "Wr ");
426
427 // Check that endpoint was in Sending state
428 if( pEndpoint->state == UDP_ENDPOINT_SENDING ) {
429
430 // End of transfer ?
431 if( UDPHS_IsTransferFinished(bEndpoint) ) {
432
433 trace_LOG(trace_DEBUG, "%d ", pTransfer->transferred);
434
435 pTransfer->transferred += pTransfer->buffered;
436 pTransfer->buffered = 0;
437
438 // Disable interrupt if this is not a control endpoint
439 if( AT91C_UDPHS_EPT_TYPE_CTL_EPT != (AT91C_UDPHS_EPT_TYPE&(AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG)) ) {
440
441 #ifndef DMA
442 AT91C_BASE_UDPHS->UDPHS_IEN &= ~(1<<SHIFT_INTERUPT<<bEndpoint);
443 #else
444 AT91C_BASE_UDPHS->UDPHS_IEN &= ~(1<<SHIFT_DMA<<bEndpoint);
445 #endif
446 }
447 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLDIS = AT91C_UDPHS_TX_PK_RDY;
448
449 UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS);
450 }
451 else {
452
453 // Transfer remaining data
454 trace_LOG(trace_DEBUG, "%d ", pEndpoint->size);
455 pTransfer->transferred += pEndpoint->size;
456 pTransfer->buffered -= pEndpoint->size;
457
458 // Send next packet
459 UDPHS_WritePayload(bEndpoint);
460 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTSETSTA = AT91C_UDPHS_TX_PK_RDY;
461 }
462 }
463 else {
464
465 trace_LOG(trace_FATAL, "Error Wr");
466 }
467 }
468
469 // OUT packet received
470 if( AT91C_UDPHS_RX_BK_RDY == (status & AT91C_UDPHS_RX_BK_RDY) ) {
471
472 trace_LOG(trace_DEBUG, "Rd ");
473
474 // Check that the endpoint is in Receiving state
475 if (pEndpoint->state != UDP_ENDPOINT_RECEIVING) {
476
477 // Endpoint is NOT in Read state
478 if( (0 == (AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG & AT91C_UDPHS_EPT_TYPE))
479 && (0 == (status & AT91C_UDPHS_BYTE_COUNT)) ) {
480
481 // Control endpoint, 0 bytes received
482 // Acknowledge the data and finish the current transfer
483 trace_LOG(trace_DEBUG, "Ack ");
484 UDPHS_ClearRxFlag(bEndpoint);
485
486 UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS);
487 }
488 // Check if the data has been STALLed
489 else if( AT91C_UDPHS_FRCESTALL == (status & AT91C_UDPHS_FRCESTALL)) {
490
491 // Discard STALLed data
492 trace_LOG(trace_DEBUG, "Discard ");
493 UDPHS_ClearRxFlag(bEndpoint);
494 }
495 // NAK the data
496 else {
497
498 trace_LOG(trace_DEBUG, "Nak ");
499 #ifndef DMA
500 AT91C_BASE_UDPHS->UDPHS_IEN &= ~(1<<SHIFT_INTERUPT<<bEndpoint);
501 #else
502 AT91C_BASE_UDPHS->UDPHS_IEN &= ~(1<<SHIFT_DMA<<bEndpoint);
503 #endif
504 }
505 }
506 else {
507
508 // Endpoint is in Read state
509 // Retrieve data and store it into the current transfer buffer
510 wPacketSize = (unsigned short)((status & AT91C_UDPHS_BYTE_COUNT)>>20);
511
512 trace_LOG(trace_DEBUG, "%d ", wPacketSize);
513 UDPHS_ReadPayload(bEndpoint, wPacketSize);
514 UDPHS_ClearRxFlag(bEndpoint);
515
516 // Check if the transfer is finished
517 if ((pTransfer->remaining == 0) || (wPacketSize < pEndpoint->size)) {
518
519 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLDIS = AT91C_UDPHS_RX_BK_RDY;
520
521 // Disable interrupt if this is not a control endpoint
522 if( AT91C_UDPHS_EPT_TYPE_CTL_EPT != (AT91C_UDPHS_EPT_TYPE & (AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG)) ) {
523
524 #ifndef DMA
525 AT91C_BASE_UDPHS->UDPHS_IEN &= ~(1<<SHIFT_INTERUPT<<bEndpoint);
526 #else
527 AT91C_BASE_UDPHS->UDPHS_IEN &= ~(1<<SHIFT_DMA<<bEndpoint);
528 #endif
529 }
530 UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS);
531 }
532 }
533 }
534
535 // STALL sent
536 if( AT91C_UDPHS_STALL_SNT == (status & AT91C_UDPHS_STALL_SNT) ) {
537
538 trace_LOG(trace_WARNING, "Sta 0x%X [%d] ", status, bEndpoint);
539
540 // Acknowledge the stall flag
541 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCLRSTA = AT91C_UDPHS_STALL_SNT;
542
543 // If the endpoint is not halted, clear the STALL condition
544 if (pEndpoint->state != UDP_ENDPOINT_HALTED) {
545
546 trace_LOG(trace_WARNING, "_ " );
547 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCLRSTA = AT91C_UDPHS_FRCESTALL;
548 }
549 }
550
551 // SETUP packet received
552 if( AT91C_UDPHS_RX_SETUP == (status & AT91C_UDPHS_RX_SETUP) ) {
553
554 trace_LOG(trace_DEBUG, "Stp ");
555
556 // If a transfer was pending, complete it
557 // Handles the case where during the status phase of a control write
558 // transfer, the host receives the device ZLP and ack it, but the ack
559 // is not received by the device
560 if ((pEndpoint->state == UDP_ENDPOINT_RECEIVING)
561 || (pEndpoint->state == UDP_ENDPOINT_SENDING)) {
562
563 UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS);
564 }
565 // Copy the setup packet
566 UDPHS_ReadRequest(&request);
567
568 // Acknowledge setup packet
569 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCLRSTA = AT91C_UDPHS_RX_SETUP;
570
571 // Forward the request to the upper layer
572 USBDCallbacks_RequestReceived(&request);
573 }
574
575 }
576
577 //------------------------------------------------------------------------------
578 // Interrupt service routine
579 //------------------------------------------------------------------------------
580 #ifdef DMA
581 //----------------------------------------------------------------------------
582 // \fn UDPHS_DmaHandler
583 // \brief This function (ISR) handles dma interrupts
584 //----------------------------------------------------------------------------
585 static void UDPHS_DmaHandler( unsigned char bEndpoint )
586 {
587 Endpoint *pEndpoint = &(endpoints[bEndpoint]);
588 Transfer *pTransfer = &(pEndpoint->transfer);
589 unsigned int status;
590 unsigned char result = USBD_STATUS_SUCCESS;
591
592 status = AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMASTATUS;
593 trace_LOG(trace_DEBUG, "Dma Ept%d ", bEndpoint);
594
595 // Disable DMA interrupt to avoid receiving 2 interrupts (B_EN and TR_EN)
596 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL &=
597 ~(AT91C_UDPHS_END_TR_EN | AT91C_UDPHS_END_B_EN);
598
599 AT91C_BASE_UDPHS->UDPHS_IEN &= ~(1 << SHIFT_DMA << bEndpoint);
600
601 if( AT91C_UDPHS_END_BF_ST == (status & AT91C_UDPHS_END_BF_ST) ) {
602
603 trace_LOG(trace_DEBUG, "EndBuffer ");
604
605 // BUFF_COUNT holds the number of untransmitted bytes.
606 // BUFF_COUNT is equal to zero in case of good transfer
607 pTransfer->transferred = pTransfer->buffered
608 - ((status & AT91C_UDPHS_BUFF_COUNT) >> 16);
609 pTransfer->buffered = ((status & AT91C_UDPHS_BUFF_COUNT) >> 16);
610
611 pTransfer->remaining -= pTransfer->transferred;
612
613 trace_LOG(trace_DEBUG, "\n\rR:%d ", pTransfer->remaining );
614 trace_LOG(trace_DEBUG, "B:%d ", pTransfer->buffered );
615 trace_LOG(trace_DEBUG, "T:%d ", pTransfer->transferred );
616
617 if( (pTransfer->remaining + pTransfer->buffered) > 0 ) {
618
619 // Prepare an other transfer
620 if( pTransfer->remaining > DMA_MAX_FIFO_SIZE ) {
621
622 pTransfer->buffered = DMA_MAX_FIFO_SIZE;
623 }
624 else {
625 pTransfer->buffered = pTransfer->remaining;
626 }
627
628 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMAADDRESS =
629 (unsigned int)((pTransfer->pData)+(pTransfer->buffered));
630
631 // Clear unwanted interrupts
632 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMASTATUS;
633
634 // Enable DMA endpoint interrupt
635 AT91C_BASE_UDPHS->UDPHS_IEN |= (1 << SHIFT_DMA << bEndpoint);
636 // DMA config for receive the good size of buffer, or an error buffer
637
638 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = 0; // raz
639 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL =
640 ( ((pTransfer->buffered << 16) & AT91C_UDPHS_BUFF_COUNT)
641 | AT91C_UDPHS_END_TR_EN
642 | AT91C_UDPHS_END_TR_IT
643 | AT91C_UDPHS_END_B_EN
644 | AT91C_UDPHS_END_BUFFIT
645 | AT91C_UDPHS_CHANN_ENB );
646 }
647 }
648 else if( AT91C_UDPHS_END_TR_ST == (status & AT91C_UDPHS_END_TR_ST) ) {
649
650 trace_LOG(trace_DEBUG, "EndTransf ");
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