📄 board_memories.lst
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\ In section .rodata, align 4
\ ??pinsSdram:
\ 00000000 0000803F00F4 DC32 1065353216, 0FFFFF400H
\ FFFF
\ 00000008 02010000 DC8 2, 1, 0, 0
\ 0000000C FFFF030000F6 DC32 262143, 0FFFFF600H
\ FFFF
\ 00000014 03010000 DC8 3, 1, 0, 0
\ 00000018 FFFF000000F8 DC32 65535, 0FFFFF800H
\ FFFF
\ 00000020 04000000 DC8 4, 0, 0, 0
201
202 //------------------------------------------------------------------------------
203 /// Configures the EBI for NandFlash access. Pins must be configured after or
204 /// before calling this function.
205 //------------------------------------------------------------------------------
\ In section .text, align 4, keep-with-next
206 void BOARD_ConfigureNandFlash(unsigned char busWidth)
207 {
208 // Configure EBI
209 AT91C_BASE_EBI->EBI_CSA |= AT91C_EBI_CS3A_SMC_NandFlash;
\ BOARD_ConfigureNandFlash:
\ 00000000 7F10E0E3 MVN R1,#+127
\ 00000004 001091E5 LDR R1,[R1, #+0]
\ 00000008 081091E3 ORRS R1,R1,#0x8
\ 0000000C 7F20E0E3 MVN R2,#+127
\ 00000010 001082E5 STR R1,[R2, #+0]
210
211 #define AT91C_SMC2_NWS_2 ((unsigned int) 1 << 0)
212 #define AT91C_SMC2_TDF_2_CYCLES ((unsigned int) 2 << 8)
213 #define AT91C_SMC2_BAT_8BIT ((unsigned int) 0 << 12)
214 #define AT91C_SMC2_DRP_STANDARD ((unsigned int) 0 << 15)
215 #define AT91C_SMC2_RWSETUP_0_CYCLE ((unsigned int) 0 << 24)
216 #define AT91C_SMC2_RWHOLD_1_CYCLE ((unsigned int) 1 << 28)
217
218 // Configure SMC
219 AT91C_BASE_SMC->SMC2_CSR[3] =
220 AT91C_SMC2_NWS_2 // 2 wait states required required by the NAND Flash device
221 | AT91C_SMC2_WSEN // NWS register enabled
222 | AT91C_SMC2_TDF_2_CYCLES // 2 Data Float Time Cycles required by the NAND Flash device
223 | AT91C_SMC2_BAT_8BIT // 1 8-bit device connected over the bus
224 | AT91C_SMC2_DBW_8 // 8-bit Data Bus Width
225 | AT91C_SMC2_DRP_STANDARD // Standard Read protocol required by the NAND Flash device
226 | AT91C_SMC2_ACSS_STANDARD // Standard address to chip select
227 | AT91C_SMC2_RWSETUP_0_CYCLE // 0 Read/Write Setup time required by the Nand Flash Device
228 | AT91C_SMC2_RWHOLD_1_CYCLE; // 1 Read/Write Setup time required by the ECC controller
\ 00000014 6310E0E3 MVN R1,#+99
\ 00000018 48209FE5 LDR R2,??BOARD_ConfigureNandFlash_0 ;; 0x10004281
\ 0000001C 002081E5 STR R2,[R1, #+0]
229
230 if (busWidth == 8) {
\ 00000020 FF0010E2 ANDS R0,R0,#0xFF ;; Zero extend
\ 00000024 080050E3 CMP R0,#+8
\ 00000028 0500001A BNE ??BOARD_ConfigureNandFlash_1
231 AT91C_BASE_SMC->SMC2_CSR[3] |= AT91C_SMC2_DBW_8;
\ 0000002C 6310E0E3 MVN R1,#+99
\ 00000030 001091E5 LDR R1,[R1, #+0]
\ 00000034 401C91E3 ORRS R1,R1,#0x4000
\ 00000038 6320E0E3 MVN R2,#+99
\ 0000003C 001082E5 STR R1,[R2, #+0]
\ 00000040 070000EA B ??BOARD_ConfigureNandFlash_2
232 }
233 else if (busWidth == 16) {
\ ??BOARD_ConfigureNandFlash_1:
\ 00000044 FF0010E2 ANDS R0,R0,#0xFF ;; Zero extend
\ 00000048 100050E3 CMP R0,#+16
\ 0000004C 0400001A BNE ??BOARD_ConfigureNandFlash_2
234
235 AT91C_BASE_SMC->SMC2_CSR[3] |= AT91C_SMC2_DBW_16;
\ 00000050 6310E0E3 MVN R1,#+99
\ 00000054 001091E5 LDR R1,[R1, #+0]
\ 00000058 801D91E3 ORRS R1,R1,#0x2000
\ 0000005C 6320E0E3 MVN R2,#+99
\ 00000060 001082E5 STR R1,[R2, #+0]
236 }
237 }
\ ??BOARD_ConfigureNandFlash_2:
\ 00000064 1EFF2FE1 BX LR ;; return
\ ??BOARD_ConfigureNandFlash_0:
\ 00000068 81420010 DC32 0x10004281
238
239 //------------------------------------------------------------------------------
240 /// Configures a list of AT91S_EFC instances.
241 /// \param list Pointer to a list of AT91S_EFC instances.
242 /// \param size Size of the AT91S_EFC list.
243 /// \param numWaitStates Number of state cycles value for the EFC.
244 //------------------------------------------------------------------------------
\ In section .text, align 4, keep-with-next
245 void BOARD_ConfigureFlash48MHz(void)
246 {
247 /* Set flash wait states in the EFC
248 **********************************/
249 /* 48MHz = 1 wait state */
250 #if defined(at91sam7se512)
251 AT91C_BASE_EFC0->EFC_FMR = AT91C_MC_FWS_1FWS;
\ BOARD_ConfigureFlash48MHz:
\ 00000000 9F00E0E3 MVN R0,#+159
\ 00000004 401FA0E3 MOV R1,#+256
\ 00000008 001080E5 STR R1,[R0, #+0]
252 AT91C_BASE_EFC1->EFC_FMR = AT91C_MC_FWS_1FWS;
\ 0000000C 8F00E0E3 MVN R0,#+143
\ 00000010 401FA0E3 MOV R1,#+256
\ 00000014 001080E5 STR R1,[R0, #+0]
253 #elif defined(at91sam7se32) || defined(at91sam7se256)
254 AT91C_BASE_EFC->EFC_FMR = AT91C_MC_FWS_1FWS;
255 #else
256 #error No chip definition ?
257 #endif
258 }
\ 00000018 1EFF2FE1 BX LR ;; return
259
260 //------------------------------------------------------------------------------
261 /// Configures the EBI for NorFlash access at 48MHz.
262 /// \Param busWidth Bus width
263 //------------------------------------------------------------------------------
\ In section .text, align 4, keep-with-next
264 void BOARD_ConfigureNorFlash(unsigned char busWidth)
265 {
266
267 // Configure SMC
268 AT91C_BASE_SMC->SMC2_CSR[0] =
269 ((unsigned int) 1 << 0) // 2 wait states required required by the NAND Flash device
270 | AT91C_SMC2_WSEN // NWS register enabled
271 | ((unsigned int) 1 << 8) // 2 Data Float Time Cycles required by the NAND Flash device
272 | AT91C_SMC2_BAT_8BIT // 1 8-bit device connected over the bus
273 | ((unsigned int) 0 << 12) // 8-bit Data Bus Width
274 | ((unsigned int) 0 << 15) // Standard Read protocol required by the NAND Flash device
275 | AT91C_SMC2_ACSS_STANDARD // Standard address to chip select
276 | ((unsigned int) 1 << 24) // 1 Read/Write Setup time required by the Nand Flash Device
277 | ((unsigned int) 7 << 28); // 1 Read/Write Setup time required by the ECC controller
\ BOARD_ConfigureNorFlash:
\ 00000000 6F10E0E3 MVN R1,#+111
\ 00000004 48209FE5 LDR R2,??BOARD_ConfigureNorFlash_0 ;; 0x71000181
\ 00000008 002081E5 STR R2,[R1, #+0]
278
279 if (busWidth == 8) {
\ 0000000C FF0010E2 ANDS R0,R0,#0xFF ;; Zero extend
\ 00000010 080050E3 CMP R0,#+8
\ 00000014 0500001A BNE ??BOARD_ConfigureNorFlash_1
280 AT91C_BASE_SMC->SMC2_CSR[0] |= AT91C_SMC2_DBW_8;
\ 00000018 6F10E0E3 MVN R1,#+111
\ 0000001C 001091E5 LDR R1,[R1, #+0]
\ 00000020 401C91E3 ORRS R1,R1,#0x4000
\ 00000024 6F20E0E3 MVN R2,#+111
\ 00000028 001082E5 STR R1,[R2, #+0]
\ 0000002C 070000EA B ??BOARD_ConfigureNorFlash_2
281 }
282 else if (busWidth == 16) {
\ ??BOARD_ConfigureNorFlash_1:
\ 00000030 FF0010E2 ANDS R0,R0,#0xFF ;; Zero extend
\ 00000034 100050E3 CMP R0,#+16
\ 00000038 0400001A BNE ??BOARD_ConfigureNorFlash_2
283
284 AT91C_BASE_SMC->SMC2_CSR[0] |= AT91C_SMC2_DBW_16;
\ 0000003C 6F10E0E3 MVN R1,#+111
\ 00000040 001091E5 LDR R1,[R1, #+0]
\ 00000044 801D91E3 ORRS R1,R1,#0x2000
\ 00000048 6F20E0E3 MVN R2,#+111
\ 0000004C 001082E5 STR R1,[R2, #+0]
285 }
286 }
\ ??BOARD_ConfigureNorFlash_2:
\ 00000050 1EFF2FE1 BX LR ;; return
\ ??BOARD_ConfigureNorFlash_0:
\ 00000054 81010071 DC32 0x71000181
287
Maximum stack usage in bytes:
Function .cstack
-------- -------
BOARD_ConfigureFlash48MHz 0
BOARD_ConfigureNandFlash 0
BOARD_ConfigureNorFlash 0
BOARD_ConfigureSdram 16
BOARD_GetRemap 0
BOARD_RemapFlash 8
BOARD_RemapRam 8
Section sizes:
Function/Label Bytes
-------------- -----
BOARD_GetRemap 72
BOARD_RemapFlash 36
BOARD_RemapRam 36
BOARD_ConfigureSdram 400
pinsSdram 36
BOARD_ConfigureNandFlash 108
BOARD_ConfigureFlash48MHz 28
BOARD_ConfigureNorFlash 88
36 bytes in section .rodata
768 bytes in section .text
768 bytes of CODE memory
36 bytes of CONST memory
Errors: none
Warnings: 1
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