📄 board_memories.lst
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\ 00000000 01402DE9 PUSH {R0,LR}
113 if (BOARD_GetRemap() != BOARD_RAM) {
\ 00000004 ........ BL BOARD_GetRemap
\ 00000008 010050E3 CMP R0,#+1
\ 0000000C 0200000A BEQ ??BOARD_RemapRam_0
114
115 AT91C_BASE_MC->MC_RCR = AT91C_MC_RCB;
\ 00000010 FF00E0E3 MVN R0,#+255
\ 00000014 0110A0E3 MOV R1,#+1
\ 00000018 001080E5 STR R1,[R0, #+0]
116 }
117 }
\ ??BOARD_RemapRam_0:
\ 0000001C 0050BDE8 POP {R12,LR}
\ 00000020 1EFF2FE1 BX LR ;; return
118
119 //------------------------------------------------------------------------------
120 /// Initializes the SDRAM controller so the external SDRAM chip connected to the
121 /// EBI is accessible. The EBI pins for the SDRAM must be configured prior to
122 /// calling this function.
123 //------------------------------------------------------------------------------
\ In section .text, align 4, keep-with-next
124 void BOARD_ConfigureSdram()
125 {
\ BOARD_ConfigureSdram:
\ 00000000 13402DE9 PUSH {R0,R1,R4,LR}
126 volatile unsigned int i;
127 static const Pin pinsSdram[] = {PINS_SDRAM};
128 volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
\ 00000004 8005A0E3 MOV R0,#+536870912
\ 00000008 0040B0E1 MOVS R4,R0
129
130 // Enable corresponding PIOs
131 PIO_Configure(pinsSdram, PIO_LISTSIZE(pinsSdram));
\ 0000000C 0310A0E3 MOV R1,#+3
\ 00000010 6C019FE5 LDR R0,??BOARD_ConfigureSdram_0 ;; ??pinsSdram
\ 00000014 ........ BL PIO_Configure
132
133 // Enable EBI chip select for the SDRAM
134 WRITE(AT91C_BASE_EBI, EBI_CSA, AT91C_EBI_CS1A_SDRAMC);
\ 00000018 7F00E0E3 MVN R0,#+127
\ 0000001C 0210A0E3 MOV R1,#+2
\ 00000020 001080E5 STR R1,[R0, #+0]
135
136 #define AT91C_SDRC_NC_9 (0x1)
137 #define AT91C_SDRC_NR_13 (0x2 << 2)
138 #define AT91C_SDRC_CAS_2 (0x2 << 5)
139 #define AT91C_SDRC_NB_4_BANKS (0x1 << 4)
140 #define AT91C_SDRC_TWR_2 (0x2 << 7)
141 #define AT91C_SDRC_TRC_4 (0x4 << 11)
142 #define AT91C_SDRC_TRP_4 (0x4 << 15)
143 #define AT91C_SDRC_TRCD_2 (0x2 << 19)
144 #define AT91C_SDRC_TRAS_3 (0x3 << 23)
145 #define AT91C_SDRC_TXSR_4 (0x4 << 27)
146
147 // CFG Control Register
148 WRITE(AT91C_BASE_SDRC, SDRC_CR, AT91C_SDRC_NC_9
149 | AT91C_SDRC_NR_13
150 | AT91C_SDRC_CAS_2
151 | AT91C_SDRC_NB_4_BANKS
152 | AT91C_SDRC_TWR_2
153 | AT91C_SDRC_TRC_4
154 | AT91C_SDRC_TRP_4
155 | AT91C_SDRC_TRCD_2
156 | AT91C_SDRC_TRAS_3
157 | AT91C_SDRC_TXSR_4);
\ 00000024 4700E0E3 MVN R0,#+71
\ 00000028 58119FE5 LDR R1,??BOARD_ConfigureSdram_0+0x4 ;; 0x21922159
\ 0000002C 001080E5 STR R1,[R0, #+0]
158
159 for (i = 0; i < 1000; i++);
\ 00000030 0010A0E3 MOV R1,#+0
\ 00000034 00108DE5 STR R1,[SP, #+0]
\ ??BOARD_ConfigureSdram_1:
\ 00000038 00009DE5 LDR R0,[SP, #+0]
\ 0000003C FA0F50E3 CMP R0,#+1000
\ 00000040 0300002A BCS ??BOARD_ConfigureSdram_2
\ 00000044 00009DE5 LDR R0,[SP, #+0]
\ 00000048 010090E2 ADDS R0,R0,#+1
\ 0000004C 00008DE5 STR R0,[SP, #+0]
\ 00000050 F8FFFFEA B ??BOARD_ConfigureSdram_1
160
161 WRITE(AT91C_BASE_SDRC, SDRC_MR, AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_NOP_CMD); // Perform NOP
\ ??BOARD_ConfigureSdram_2:
\ 00000054 4F00E0E3 MVN R0,#+79
\ 00000058 1110A0E3 MOV R1,#+17
\ 0000005C 001080E5 STR R1,[R0, #+0]
162 pSdram[0] = 0x00000000;
\ 00000060 0000A0E3 MOV R0,#+0
\ 00000064 000084E5 STR R0,[R4, #+0]
163
164 WRITE(AT91C_BASE_SDRC, SDRC_MR, AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_PRCGALL_CMD); // Set PRCHG AL
\ 00000068 4F00E0E3 MVN R0,#+79
\ 0000006C 1210A0E3 MOV R1,#+18
\ 00000070 001080E5 STR R1,[R0, #+0]
165 pSdram[0] = 0x00000000; // Perform PRCHG
\ 00000074 0000A0E3 MOV R0,#+0
\ 00000078 000084E5 STR R0,[R4, #+0]
166
167 for (i = 0; i < 10000; i++);
\ 0000007C 0010A0E3 MOV R1,#+0
\ 00000080 00108DE5 STR R1,[SP, #+0]
\ ??BOARD_ConfigureSdram_3:
\ 00000084 00009DE5 LDR R0,[SP, #+0]
\ 00000088 1010A0E3 MOV R1,#+16
\ 0000008C 9C1D81E3 ORR R1,R1,#0x2700
\ 00000090 010050E1 CMP R0,R1
\ 00000094 0300002A BCS ??BOARD_ConfigureSdram_4
\ 00000098 00009DE5 LDR R0,[SP, #+0]
\ 0000009C 010090E2 ADDS R0,R0,#+1
\ 000000A0 00008DE5 STR R0,[SP, #+0]
\ 000000A4 F6FFFFEA B ??BOARD_ConfigureSdram_3
168
169 WRITE(AT91C_BASE_SDRC, SDRC_MR, AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD); // Set 1st CBR
\ ??BOARD_ConfigureSdram_4:
\ 000000A8 4F00E0E3 MVN R0,#+79
\ 000000AC 1410A0E3 MOV R1,#+20
\ 000000B0 001080E5 STR R1,[R0, #+0]
170 pSdram[1] = 0x00000001; // Perform CBR
\ 000000B4 0100A0E3 MOV R0,#+1
\ 000000B8 040084E5 STR R0,[R4, #+4]
171
172 WRITE(AT91C_BASE_SDRC, SDRC_MR, AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD); // Set 2 CBR
\ 000000BC 4F00E0E3 MVN R0,#+79
\ 000000C0 1410A0E3 MOV R1,#+20
\ 000000C4 001080E5 STR R1,[R0, #+0]
173 pSdram[2] = 0x00000002; // Perform CBR
\ 000000C8 0200A0E3 MOV R0,#+2
\ 000000CC 080084E5 STR R0,[R4, #+8]
174
175 WRITE(AT91C_BASE_SDRC, SDRC_MR, AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD); // Set 3 CBR
\ 000000D0 4F00E0E3 MVN R0,#+79
\ 000000D4 1410A0E3 MOV R1,#+20
\ 000000D8 001080E5 STR R1,[R0, #+0]
176 pSdram[3] = 0x00000003; // Perform CBR
\ 000000DC 0300A0E3 MOV R0,#+3
\ 000000E0 0C0084E5 STR R0,[R4, #+12]
177
178 WRITE(AT91C_BASE_SDRC, SDRC_MR, AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD); // Set 4 CBR
\ 000000E4 4F00E0E3 MVN R0,#+79
\ 000000E8 1410A0E3 MOV R1,#+20
\ 000000EC 001080E5 STR R1,[R0, #+0]
179 pSdram[4] = 0x00000004; // Perform CBR
\ 000000F0 0400A0E3 MOV R0,#+4
\ 000000F4 100084E5 STR R0,[R4, #+16]
180
181 WRITE(AT91C_BASE_SDRC, SDRC_MR, AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD); // Set 5 CBR
\ 000000F8 4F00E0E3 MVN R0,#+79
\ 000000FC 1410A0E3 MOV R1,#+20
\ 00000100 001080E5 STR R1,[R0, #+0]
182 pSdram[5] = 0x00000005; // Perform CBR
\ 00000104 0500A0E3 MOV R0,#+5
\ 00000108 140084E5 STR R0,[R4, #+20]
183
184 WRITE(AT91C_BASE_SDRC, SDRC_MR, AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD); // Set 6 CBR
\ 0000010C 4F00E0E3 MVN R0,#+79
\ 00000110 1410A0E3 MOV R1,#+20
\ 00000114 001080E5 STR R1,[R0, #+0]
185 pSdram[6] = 0x00000006; // Perform CBR
\ 00000118 0600A0E3 MOV R0,#+6
\ 0000011C 180084E5 STR R0,[R4, #+24]
186
187 WRITE(AT91C_BASE_SDRC, SDRC_MR, AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD); // Set 7 CBR
\ 00000120 4F00E0E3 MVN R0,#+79
\ 00000124 1410A0E3 MOV R1,#+20
\ 00000128 001080E5 STR R1,[R0, #+0]
188 pSdram[7] = 0x00000007; // Perform CBR
\ 0000012C 0700A0E3 MOV R0,#+7
\ 00000130 1C0084E5 STR R0,[R4, #+28]
189
190 WRITE(AT91C_BASE_SDRC, SDRC_MR, AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD); // Set 8 CBR
\ 00000134 4F00E0E3 MVN R0,#+79
\ 00000138 1410A0E3 MOV R1,#+20
\ 0000013C 001080E5 STR R1,[R0, #+0]
191 pSdram[8] = 0x00000008; // Perform CBR
\ 00000140 0800A0E3 MOV R0,#+8
\ 00000144 200084E5 STR R0,[R4, #+32]
192
193 WRITE(AT91C_BASE_SDRC, SDRC_MR, AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_LMR_CMD); // Set LMR operation
\ 00000148 4F00E0E3 MVN R0,#+79
\ 0000014C 1310A0E3 MOV R1,#+19
\ 00000150 001080E5 STR R1,[R0, #+0]
194 pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
\ 00000154 30009FE5 LDR R0,??BOARD_ConfigureSdram_0+0x8 ;; 0xcafedede
\ 00000158 240084E5 STR R0,[R4, #+36]
195
196 WRITE(AT91C_BASE_SDRC, SDRC_TR, AT91C_SDRC_DBW_16_BITS | (BOARD_MCK * 7) / 1000000); // Set Refresh Timer
\ 0000015C 4B00E0E3 MVN R0,#+75
\ 00000160 541FA0E3 MOV R1,#+336
\ 00000164 001080E5 STR R1,[R0, #+0]
197
198 WRITE(AT91C_BASE_SDRC, SDRC_MR, AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_NORMAL_CMD); // Set Normal mode
\ 00000168 4F00E0E3 MVN R0,#+79
\ 0000016C 1010A0E3 MOV R1,#+16
\ 00000170 001080E5 STR R1,[R0, #+0]
199 pSdram[0] = 0x00000000; // Perform Normal mode
\ 00000174 0000A0E3 MOV R0,#+0
\ 00000178 000084E5 STR R0,[R4, #+0]
200 }
\ 0000017C 1C40BDE8 POP {R2-R4,LR}
\ 00000180 1EFF2FE1 BX LR ;; return
\ ??BOARD_ConfigureSdram_0:
\ 00000184 ........ DC32 ??pinsSdram
\ 00000188 59219221 DC32 0x21922159
\ 0000018C DEDEFECA DC32 0xcafedede
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