📄 186ecmem.inc
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;************************************************************************
; *
; PSEUDO VARIABLES TO REPRESENT INTERNAL *
; REGISTERS OF THE PROCESSOR 80C18xEC. *
; *
;************************************************************************
; Modify the PCB_BASE symbol to represent
; the contents of the Relocation register (RELREG)
;
IFNDEF PCB_BASE
PCB_BASE EQU 0FF00H
ENDIF
RELREG_OFFSET EQU 0A8H
; Define Macro for accessing the 186 registers. Using these macros
; allows a user to move between I/O space and memory space easily.
Set186Register MACRO reg,val
mov ax,seg reg
mov es,ax
mov ax,val
mov word ptr es:reg,ax
ENDM
Set186RegisterByte MACRO reg,val
mov ax,seg reg
mov es,ax
mov al,val
mov byte ptr es:reg,al
ENDM
Set186RegisterAX MACRO reg
mov cx,seg reg
mov es,cx
mov word ptr es:reg, ax
ENDM
Get186Register MACRO reg
mov ax,seg reg
mov es,ax
mov ax,word ptr es:reg
ENDM
ECPCB SEGMENT AT PCB_BASE
; INTERRUPT CONTROL REGISTERS
ORG 0H
MPICP0 DW ? ; MASTER 8259A MODULE A0=0
MPICP1 DW ? ; MASTER 8259A MODULE A0=1
SPICP0 DW ? ; SLAVE 8259A MODULE A0=0
SPICP1 DW ? ; SLAVE 8259A MODULE A0=1
RES1 DW ?
SCUIRL DW ? ; SCU INTERRUPT REQUEST LATCH
DMAIRL DW ? ; DMA " " "
TIMIRL DW ? ; TIMER " " "
; WATCHDOG TIMER REGISTERS
ORG 20H
WDTRLDH DW ? ; WDT RELOAD VALUE (HIGH 16 BITS)
WDTRLDL DW ? ; WDT RELOAD VALUE (LOW 16 BITS)
WDTCNTH DW ? ; WDT COUNT VALUE (HIGH 16 BITS)
WDTCNTL DW ? ; WDT COUNT VALUE (LOW 16 BITS)
WDTCLR DW ? ; WDT CLEAR REGISTER
WDTDIS DW ? ; WDT DISABLE REGISTER
; TIMER CONTROL REGISTERS
ORG 30H
T0CNT DW ? ; TIMER 0 COUNT
T0CMPA DW ? ; TIMER 0 COMPARE A
T0CMPB DW ? ; TIMER 0 COMPARE B
T0CON DW ? ; TIMER 0 CONTROL
T1CNT DW ? ; TIMER 1 COUNT
T1CMPA DW ? ; TIMER 1 COMPARE A
T1CMPB DW ? ; TIMER 1 COMPARE B
T1CON DW ? ; TIMER 1 CONTROL
T2CNT DW ? ; TIMER 2 COUNT
T2CMPA DW ? ; TIMER 2 COMPARE A
T2RESV DW ? ; RESERVED
T2CON DW ? ; TIMER 2 CONTROL
; INPUT/OUTPUT PORT UNIT REGISTERS
ORG 48H
P3DIR DW ? ; PORT 3 DIRECTION
P3PIN DW ? ; PORT 3 PIN STATE
P3CON DW ? ; PORT 3 CONTROL
P3LTCH DW ? ; PORT 3 DATA LATCH
P1DIR DW ? ; PORT 1 DIRECTION
P1PIN DW ? ; PORT 1 PIN
P1CON DW ? ; PORT 1 CONTROL
P1LTCH DW ? ; PORT 1 LATCH
P2DIR DW ? ; PORT 2 DIRECTION
P2PIN DW ? ; PORT 2 PIN
P2CON DW ? ; PORT 2 CONTROL
P2LTCH DW ? ; PORT 2 LATCH
; SERIAL COMMUNICATION UNIT REGISTERS
ORG 60H
B0CMP DW ? ; CHANNEL 0 BAUD COMPARE
B0CNT DW ? ; CHANNEL 0 BAUD COUNT
S0CON DW ? ; CHANNEL 0 CONTROL
S0STS DW ? ; CHANNEL 0 STATUS
R0BUF DW ? ; CHANNEL 0 RECEIVE BUFFER
T0BUF DW ? ; CHANNEL 0 TRANSMIT BUFFER
SRESV1 DW ?,? ; RESERVED LOCATIONS
B1CMP DW ? ; CHANNEL 1 BAUD COMPARE
B1CNT DW ? ; CHANNEL 1 BAUD COUNT
S1CON DW ? ; CHANNEL 1 CONTROL
S1STS DW ? ; CHANNEL 1 STATUS
R1BUF DW ? ; CHANNEL 1 RECEIVE BUFFER
T1BUF DW ? ; CHANNEL 1 TRANSMIT BUFFER
; CHIP SELECT UNIT REGISTERS
ORG 80H
GCS0ST DW ? ; GLOBAL CHIP SELECT 0 START
GCS0SP DW ? ; GLOBAL CHIP SELECT 0 STOP
GCS1ST DW ? ; GLOBAL CHIP SELECT 1 START
GCS1SP DW ? ; GLOBAL CHIP SELECT 1 STOP
GCS2ST DW ? ; GLOBAL CHIP SELECT 2 START
GCS2SP DW ? ; GLOBAL CHIP SELECT 2 STOP
GCS3ST DW ? ; GLOBAL CHIP SELECT 3 START
GCS3SP DW ? ; GLOBAL CHIP SELECT 3 STOP
GCS4ST DW ? ; GLOBAL CHIP SELECT 4 START
GCS4SP DW ? ; GLOBAL CHIP SELECT 4 STOP
GCS5ST DW ? ; GLOBAL CHIP SELECT 5 START
GCS5SP DW ? ; GLOBAL CHIP SELECT 5 STOP
GCS6ST DW ? ; GLOBAL CHIP SELECT 6 START
GCS6SP DW ? ; GLOBAL CHIP SELECT 6 STOP
GCS7ST DW ? ; GLOBAL CHIP SELECT 7 START
GCS7SP DW ? ; GLOBAL CHIP SELECT 7 STOP
LCSST DW ? ; LOWER CHIP SELECT START
LCSSP DW ? ; LOWER CHIP SELECT STOP
UCSST DW ? ; UPPER CHIP SELECT START
UCSSP DW ? ; UPPER CHIP SELECT STOP
RELREG DW ? ; PERIPHERAL CONTROL BLOCK RELOCATION REGISTER
; REFRESH CONTROL UNIT REGISTERS
ORG 0B0H
RFBASE DW ? ; REFRESH BASE ADDRESS
RFTIME DW ? ; REFRESH COUNTER
RFCON DW ? ; REFRESH CONTROL
RFADDR DW ? ; REFRESH ADDRESS
; POWER MANAGEMENT CONTROL REGISTERS
ORG 0B8H
PWRCON DW ? ; IDLE AND POWERDOWN CONTROL
RES2 DW ?
STEPID DW ? ; STEPPING ID
PWRSAV DW ? ; POWER SAVE
; DMA UNIT REGISTERS
ORG 0C0H
D0SRCL DW ? ; DMA 0 SOURCE LOW
D0SRCH DW ? ; DMA 0 SOURCE HIGH
D0DSTL DW ? ; DMA 0 DESTINATION LOW
D0DSTH DW ? ; DMA 0 DESTINATION HIGH
D0TC DW ? ; DMA 0 TERMINAL COUNT
D0CON DW ? ; DMA 0 CONTROL
DMAPRI DW ? ; INTERMODULE PRIORITY AND IDRQ MUX
DMAHALT DW ? ; HALT CONTROL FOR DMA UNITS
D1SRCL DW ? ; DMA 1 SOURCE LOW
D1SRCH DW ? ; DMA 1 SOURCE HIGH
D1DSTL DW ? ; DMA 1 DESTINATION LOW
D1DSTH DW ? ; DMA 1 DESTINATION HIGH
D1TC DW ? ; DMA 1 TERMINAL COUNT
D1CON DW ? ; DMA 1 CONTROL
ORG 0E0H
D2SRCL DW ? ; DMA 2 SOURCE LOW
D2SRCH DW ? ; DMA 2 SOURCE HIGH
D2DSTL DW ? ; DMA 2 DESTINATION LOW
D2DSTH DW ? ; DMA 2 DESTINATION HIGH
D2TC DW ? ; DMA 2 TERMINAL COUNT
D2CON DW ? ; DMA 2 CONTROL
ORG 0F0H
D3SRCL DW ? ; DMA 3 SOURCE LOW
D3SRCH DW ? ; DMA 3 SOURCE HIGH
D3DSTL DW ? ; DMA 3 DESTINATION LOW
D3DSTH DW ? ; DMA 3 DESTINATION HIGH
D3TC DW ? ; DMA 3 TERMINAL COUNT
D3CON DW ? ; DMA 3 CONTROL
ECPCB ENDS
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