186a.cod

mcs51,2051,x86系列MCU

INCLUDE 186ecmem.inc
  $$END$
  $$IFP$ 80C186EB
INCLUDE 186ebmem.inc
  $$END$
  $$IFNP$ 80C186EB &! 80C186EC
INCLUDE 186eamem.inc
  $$END$
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
  $$IFP$ 80C186EC
INCLUDE 186ecio.inc
  $$END$
  $$IFP$ 80C186EB
INCLUDE 186ebio.inc
  $$END$
  $$IFNP$ 80C186EB &! 80C186EC
INCLUDE 186eaio.inc
  $$END$
$$END$
_TEXT    SEGMENT PUBLIC 'CODE'
    ASSUME CS:_TEXT
Init_Timer2 Proc
; Load Timer Compare Register A
    Set186Register T2CMPA, 0$$T2CMPA$H
;
; Clear Timer 2 Count Register
    Set186Register T2CNT, 0
;
; Initialize Timer 2 Control Register
; Enable =($$T2CON.15$) $%eT2CON.15$
; Inhibit = ($$T2CON.14$) Enable Change $%tT2CON.14$$NOT$ Allowed
; Interrupt = ($$T2CON.13$) $%tT2CON.13$Interrupt at MC$No Interrupt$
; Continuous Mode = ($$T2CON.0$) $%eT2CON.0$
    Set186Register T2CON, 0$$T2CON$H
    ret
Init_Timer2 ENDP
_TEXT   ENDS
END
##80C186EC Timer1#
##80C186EB Timer1#
##80C186XL Timer1#
##80C186EA Timer1#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
  $$IFP$ 80C186EC
INCLUDE 186ecmem.inc
  $$END$
  $$IFP$ 80C186EB
INCLUDE 186ebmem.inc
  $$END$
  $$IFNP$ 80C186EB &! 80C186EC
INCLUDE 186eamem.inc
  $$END$
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
  $$IFP$ 80C186EC
INCLUDE 186ecio.inc
  $$END$
  $$IFP$ 80C186EB
INCLUDE 186ebio.inc
  $$END$
  $$IFNP$ 80C186EB &! 80C186EC
INCLUDE 186eaio.inc
  $$END$
$$END$
_TEXT    SEGMENT PUBLIC 'CODE'
    ASSUME CS:_TEXT
Init_Timer1 Proc
; Load Timer Compare Register A
    Set186Register T1CMPA, 0$$T1CMPA$H
;
; Load Timer Compare Register B
    Set186Register T1CMPB, 0$$T1CMPB$H
;
; Clear Timer 1 Counter Register
    Set186Register T1CNT, 0
;
; Initialize Timer 1 Control Register
; Enable = ($$T1CON.15$) $%eT1CON.15$ 
; Inhibit = ($$T1CON.14$) Enable Change $%tT1CON.14$$NOT$ Allowed
; Interrupt = ($$T1CON.13$) $%tT1CON.13$Interrupt at MC$No Interrupt$
; Retrigger = ($$T1CON.4$) $%eT1CON.4$
; Prescaler = ($$T1CON.3$) $%eT1CON.3$
; External Clock = ($$T1CON.2$) $%tT1CON.2$External$Internal$ Clock
; Alternate Compare Register = ($$T1CON.1$) $%eT1CON.1$
; Continuous Mode = ($$T1CON.0$) $%eT1CON.0$
    Set186Register T1CON, 0$$T1CON$H
    ret
Init_Timer1 ENDP
_TEXT   ENDS
END
##80C186EC Timer0#
##80C186EB Timer0#
##80C186XL Timer0#
##80C186EA Timer0#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
  $$IFP$ 80C186EC
INCLUDE 186ecmem.inc
  $$END$
  $$IFP$ 80C186EB
INCLUDE 186ebmem.inc
  $$END$
  $$IFNP$ 80C186EB &! 80C186EC
INCLUDE 186eamem.inc
  $$END$
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
  $$IFP$ 80C186EC
INCLUDE 186ecio.inc
  $$END$
  $$IFP$ 80C186EB
INCLUDE 186ebio.inc
  $$END$
  $$IFNP$ 80C186EB &! 80C186EC
INCLUDE 186eaio.inc
  $$END$
$$END$
_TEXT    SEGMENT PUBLIC 'CODE'
    ASSUME CS:_TEXT
Init_Timer0 Proc
; Load Timer Compare Register A
    Set186Register T0CMPA, 0$$T0CMPA$H
;
; Load Timer Compare Register B
    Set186Register T0CMPB, 0$$T0CMPB$H
;
; Clear Timer 0 Count Register
    Set186Register T0CNT, 0
;
; Initialize Timer 0 control register
; Enable = ($$T0CON.15$) $%eT0CON.15$
; Inhibit = ($$T0CON.14$) Enable Change $%tT0CON.14$$NOT$ Allowed
; Interrupt = ($$T0CON.13$) $%tT0CON.13$Interrupt at MC$No Interrupt$
; Retrigger = ($$T0CON.4$) $%eT0CON.4$
; Prescaler = ($$T0CON.3$) $%eT0CON.3$
; External Clock = ($$T0CON.2$) $%tT0CON.2$External$Internal$ Clock
; Alternate Compare Register = ($$T0CON.1$) $%eT0CON.1$
; Continuous Mode = ($$T0CON.0$) $%eT0CON.0$
    Set186Register T0CON, 0$$T0CON$H
    ret
Init_Timer0 ENDP
_TEXT   ENDS
END
##80C186?? PCB#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
  $$IFP$ 80C186EC
INCLUDE 186ecmem.inc
  $$END$
  $$IFP$ 80C186EB
INCLUDE 186ebmem.inc
  $$END$
  $$IFNP$ 80C186EB &! 80C186EC
INCLUDE 186eamem.inc
  $$END$
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
  $$IFP$ 80C186EC
INCLUDE 186ecio.inc
  $$END$
  $$IFP$ 80C186EB
INCLUDE 186ebio.inc
  $$END$
  $$IFNP$ 80C186EB &! 80C186EC
INCLUDE 186eaio.inc
  $$END$
$$END$
_TEXT    SEGMENT PUBLIC 'CODE'
    ASSUME CS:_TEXT
Init_PCB    Proc
; Escape Trap = $%eRELREG.15$
; Memory I/O  = $%tRELREG.12$Memory$I/O$ Space
;
; Old PCB Start Address = 0FF00H (in I/O space)
$$IF$ RELREG.12
; New PCB Start Address = 0$$RELREG.0-11$00H (in memory space)
;
; Move PCB from the I/O space to memory space
$$END$
$$IFN$ RELREG.12
; New PCB Start Address = 0$$RELREG.0-7$0000H (in I/O space)
;
; Move PCB within the I/O space
$$END$
;
    mov  dx, 0FF00H + RELREG_OFFSET
    mov  al, 0$$RELREG$H
    out  dx,al
    ret
Init_PCB    ENDP
_TEXT   ENDS
END
##80C186XL CSU#
##80C186EA CSU#
##80C186XL BIU#
##80C186EA BIU#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
INCLUDE 186eamem.inc
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
INCLUDE 186eaio.inc
$$END$
_TEXT    SEGMENT PUBLIC 'CODE'
    ASSUME CS:_TEXT
Init_ChipSelects    Proc
; Initialize UCS Chip Select
;
; Bus Ready Disable = ($$UMCS.2$) Bus Ready $%tUMCS.2$Disabled$Enabled$
; Start Address = @@UMCSSTART@
; Wait States = @@UMCSWS@
    Set186Register UMCS, 0$$UMCS$H
;
; Initialize LCS Chip Select
;
; Bus Ready Disable = ($$LMCS.2$) Bus Ready $%tLMCS.2$Disabled$Enabled$
; End Address = @@LMCSEND@
; Wait States = @@LMCSWS@
    Set186Register LMCS, 0$$LMCS$H
;
; Initialize MPCS and PCS  Chip Selects
;
; MCS Block Size = @@MCSBLK@
; PCS5 and PCS6 Pin Selector = ($$MPCS.7$) $%tMPCS.7$Chip Selects$Latched Address Bits A1 & A2$
; PCS Bus Cycle Selector = ($$MPCS.6$) $%tMPCS.6$Memory$I/O$ Bus Cycles
; PCS4-PCS6 Bus Ready Disable = ($$MPCS.2$) Bus Ready $%tMPCS.2$Disabled$Enabled$
; PCS4-PCS6 Wait States = @@PCS4WS@
    Set186Register MPCS, 0$$MPCS$H
;
; Initialize MCS Chip Select
;
; Bus Ready Disable = ($$MMCS.2$) Bus Ready $%tMMCS.2$Disabled$Enabled$
; Start Address = @@MCSSTART@
; Wait States  = @@MCSWS@
    Set186Register MMCS, 0$$MMCS$H
;
; Initialize PCS Control Register
;
; Bus Ready Disable = ($$PACS.2$) Bus Ready $%tPACS.2$Disabled$Enabled$
; PCS Wait States = @@PCSWS@
; Start Address = @@PCSSTART@
    Set186Register PACS, 0$$PACS$H
    ret
Init_ChipSelects    ENDP
_TEXT   ENDS
END
##80C186EB CSU#
##80C186EC CSU#
##80C186EB BIU#
##80C186EC BIU#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
  $$IFP$ 80C186EC
INCLUDE 186ecmem.inc
  $$END$
  $$IFP$ 80C186EB
INCLUDE 186ebmem.inc
  $$END$
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
  $$IFP$ 80C186EC
INCLUDE 186ecio.inc
  $$END$
  $$IFP$ 80C186EB
INCLUDE 186ebio.inc
  $$END$
$$END$
_TEXT    SEGMENT PUBLIC 'CODE'
    ASSUME CS:_TEXT
Init_ChipSelects    Proc
;Initialize Upper Chip Select
; Initialize Start Register
;  Start Address = @@UCSSTART@
;  Wait States = @@UCSWS@
    Set186Register UCSST, 0$$UCSST$H
;
; Initialize Stop Register
;  Stop Address = @@UCSSTOP@
;  Chip Select Enable = ($$UCSSP.3$) $%eUCSSP.3$
;  Ignore Stop Address = ($$UCSSP.2$) Stop Adderss $%tUCSSP.2$Disabled$Enabled$
;  Bus Cycle Selector = ($$UCSSP.1$) $%tUCSSP.1$Memory$I/O$ Bus Cycle
;  Bus Ready Enable = ($$UCSSP.0$) Bus Ready $%eUCSSP.0$
    Set186Register UCSSP, 0$$UCSSP$H
;
;Initialize Lower Chip Select
;  Initialize Start Register
;  Start Address = @@LCSSTART@
;  Wait States = @@LCSWS@
    Set186Register LCSST, 0$$LCSST$H
;
; Initialize Stop Register
;  Stop Address = @@LCSSTOP@
;  Chip Select Enable = ($$LCSSP.3$) $%eLCSSP.3$
;  Ignore Stop Address = ($$LCSSP.2$) Stop Address $%tLCSSP.2$Disabled$Enabled$
;  Bus Cycle Selector = ($$LCSSP.1$) $%tLCSSP.1$Memory$I/O$ Bus Cycle
;  Bus Ready Enable = ($$LCSSP.0$) $%eLCSSP.0$ 
    Set186Register LCSSP, 0$$LCSSP$H
;
;Initialize GCS0
; Initialize Start Register
;  Start Address = @@GCS0START@
;  Wait States = @@GCS0WS@
    Set186Register GCS0ST, 0$$GCS0ST$H
;
; Initialize Stop Register
;  Stop Address = @@GCS0STOP@
;  Chip Select Enable = ($$GCS0SP.3$) $%eGCS0SP.3$
;  Ignore Stop Address = ($$GCS0SP.2$) Stop Address $%tGCS0SP.2$Disable$Enable$
;  Bus Cycle Selector = ($$GCS0SP.1$) $%tGCS0SP.1$Memory$I/O$ Bus Cycle
;  Bus Ready Enable = ($$GCS0SP.0$) $%eGCS0SP.0$
    Set186Register GCS0SP, 0$$GCS0SP$H
;
;Initialize GCS1
; Initialize Start Register
;  Start Address = @@GCS1START@
;  Wait States = @@GCS1WS@
    Set186Register GCS1ST, 0$$GCS1ST$H
;
; Initialize Stop Register
;  Stop Address = @@GCS1STOP@
;  Chip Select Enable = ($$GCS1SP.3$) $%eGCS1SP.3$
;  Ignore Stop Address = ($$GCS1SP.2$) Stop Address $%tGCS1SP.2$Disable$Enable$
;  Bus Cycle Selector = ($$GCS1SP.1$) $%tGCS1SP.1$Memory$I/O$ Bus Cycle
;  Bus Ready Enable = ($$GCS1SP.0$) $%eGCS1SP.0$
    Set186Register GCS1SP, 0$$GCS1SP$H
;
;Initialize GCS2
; Initialize Start Register
;  Start Address = @@GCS2START@
;  Wait States = @@GCS2WS@
    Set186Register GCS2ST, 0$$GCS2ST$H
;
; Initialize Stop Register
;  Stop Address = @@GCS2STOP@
;  Chip Select Enable = ($$GCS2SP.3$) $%eGCS2SP.3$
;  Ignore Stop Address = ($$GCS2SP.2$) Stop Address $%tGCS2SP.2$Disable$Enable$
;  Bus Cycle Selector = ($$GCS2SP.1$) $%tGCS2SP.1$Memory$I/O$ Bus Cycle
;  Bus Ready Enable = ($$GCS2SP.0$) $%eGCS2SP.0$
    Set186Register GCS2SP, 0$$GCS2SP$H
;
;Initialize GCS3
; Initialize Start Register
;  Start Address = @@GCS3START@
;  Wait States = @@GCS3WS@
    Set186Register GCS3ST, 0$$GCS3ST$H
;
; Initialize Stop Register
;  Stop Address = @@GCS3STOP@
;  Chip Select Enable = ($$GCS3SP.3$) $%eGCS3SP.3$
;  Ignore Stop Address = ($$GCS3SP.2$) Stop Address $%tGCS3SP.2$Disable$Enable$
;  Bus Cycle Selector = ($$GCS3SP.1$) $%tGCS3SP.1$Memory$I/O$ Bus Cycle
;  Bus Ready Enable = ($$GCS3SP.0$) $%eGCS3SP.0$
    Set186Register GCS3SP, 0$$GCS3SP$H
;
;Initialize GCS4
; Initialize Start Register
;  Start Address = @@GCS4START@
;  Wait States = @@GCS4WS@
    Set186Register GCS4ST, 0$$GCS4ST$H
;
; Initialize Stop Register
;  Stop Address = @@GCS4STOP@
;  Chip Select Enable = ($$GCS4SP.3$) $%eGCS4SP.3$
;  Ignore Stop Address = ($$GCS4SP.2$) Stop Address $%tGCS4SP.2$Disable$Enable$
;  Bus Cycle Selector = ($$GCS4SP.1$) $%tGCS4SP.1$Memory$I/O$ Bus Cycle
;  Bus Ready Enable = ($$GCS4SP.0$) $%eGCS4SP.0$
    Set186Register GCS4SP, 0$$GCS4SP$H
;
;Initialize GCS5
; Initialize Start Register
;  Start Address = @@GCS5START@
;  Wait States = @@GCS5WS@
    Set186Register GCS5ST, 0$$GCS5ST$H
;
; Initialize Stop Register
;  Stop Address = @@GCS5STOP@
;  Chip Select Enable = ($$GCS5SP.3$) $%eGCS5SP.3$
;  Ignore Stop Address = ($$GCS5SP.2$) Stop Address $%tGCS5SP.2$Disable$Enable$
;  Bus Cycle Selector = ($$GCS5SP.1$) $%tGCS5SP.1$Memory$I/O$ Bus Cycle
;  Bus Ready Enable = ($$GCS5SP.0$) $%eGCS5SP.0$
    Set186Register GCS5SP, 0$$GCS5SP$H
;
;Initialize GCS6
; Initialize Start Register
;  Start Address = @@GCS6START@
;  Wait States = @@GCS6WS@
    Set186Register GCS6ST, 0$$GCS6ST$H
;
; Initialize Stop Register
;  Stop Address = @@GCS6STOP@
;  Chip Select Enable = ($$GCS6SP.3$) $%eGCS6SP.3$
;  Ignore Stop Address = ($$GCS6SP.2$) Stop Address $%tGCS6SP.2$Disable$Enable$
;  Bus Cycle Selector = ($$GCS6SP.1$) $%tGCS6SP.1$Memory$I/O$ Bus Cycle
;  Bus Ready Enable = ($$GCS6SP.0$) $%eGCS6SP.0$
    Set186Register GCS6SP, 0$$GCS6SP$H
;
;Initialize GCS7
; Initialize Start Register
;  Start Address = @@GCS7START@
;  Wait States = @@GCS7WS@
    Set186Register GCS7ST, 0$$GCS7ST$H
;
; Initialize Stop Register
;  Stop Address = @@GCS7STOP@
;  Chip Select Enable = ($$GCS7SP.3$) $%eGCS7SP.3$
;  Ignore Stop Address = ($$GCS7SP.2$) Stop Address $%tGCS7SP.2$Disable$Enable$
;  Bus Cycle Selector = ($$GCS7SP.1$) $%tGCS7SP.1$Memory$I/O$ Bus Cycle
;  Bus Ready Enable = ($$GCS7SP.0$) $%eGCS7SP.0$
    Set186Register GCS7SP, 0$$GCS7SP$H
    ret
Init_ChipSelects    ENDP
_TEXT   ENDS
END
##80C186EC IO1#
##80C186EB IO1#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
  $$IFP$ 80C186EC
INCLUDE 186ecmem.inc
  $$END$
  $$IFP$ 80C186EB
INCLUDE 186ebmem.inc
  $$END$
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
  $$IFP$ 80C186EC
INCLUDE 186ecio.inc
  $$END$
  $$IFP$ 80C186EB
INCLUDE 186ebio.inc
  $$END$
$$END$
_TEXT    SEGMENT PUBLIC 'CODE'
    ASSUME CS:_TEXT
Init_IO_Port1   Proc
; P1.7/GCS7 = ($$P1CON.7$) $%tP1CON.7$Chip Select Pin$I/O Pin$
; P1.6/GCS6 = ($$P1CON.6$) $%tP1CON.6$Chip Select Pin$I/O Pin$
; P1.5/GCS5 = ($$P1CON.5$) $%tP1CON.5$Chip Select Pin$I/O Pin$
; P1.4/GCS4 = ($$P1CON.4$) $%tP1CON.4$Chip Select Pin$I/O Pin$
; P1.3/GCS3 = ($$P1CON.3$) $%tP1CON.3$Chip Select Pin$I/O Pin$
; P1.2/GCS2 = ($$P1CON.2$) $%tP1CON.2$Chip Select Pin$I/O Pin$
; P1.1/GCS1 = ($$P1CON.1$) $%tP1CON.1$Chip Select Pin$I/O Pin$
; P1.0/GCS0 = ($$P1CON.0$) $%tP1CON.0$Chip Select Pin$I/O Pin$
    Set186Register P1CON, 0$$P1CON$H
    ret
Init_IO_Port1   ENDP
_TEXT   ENDS
END
##80C186EC IO2#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
INCLUDE 186ecmem.inc
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
INCLUDE 186ecio.inc
$$END$
_TEXT    SEGMENT PUBLIC 'CODE'
    ASSUME CS:_TEXT
Init_IO_Port2   Proc
; P2.7/CTS1  = ($$P2CON.7$) $%tP2CON.7$CTS1 Pin$I/O Pin$
; P2.6/BCLK1 = ($$P2CON.6$) $%tP2CON.6$BCLK1 Pin$I/O Pin$
; P2.5/BCLK0 = ($$P2CON.5$) $%tP2CON.5$TxD1 Pin$I/O Pin$
; P2.4/CTS1  = ($$P2CON.4$) $%tP2CON.4$RxD1 Pin$I/O Pin$
; P2.3/SINT1 = ($$P2CON.3$) $%tP2CON.3$CTS0 Pin$I/O Pin$
; P2.2/BLK1  = ($$P2CON.2$) $%tP2CON.2$BCLK0 Pin$I/O Pin$
; P2.1/TXD1  = ($$P2CON.1$) $%tP2CON.1$TxD0 Pin$I/O Pin$
; P2.0/RXD1  = ($$P2CON.0$) $%tP2CON.0$RxD0 Pin$I/O Pin$
    Set186Register P2CON, 0$$P2CON$H
;
; Initialize Port 2 Direction
;         Output = 1
; P2.7 = ($$P2DIR.7$) $%tP2DIR.$Input$Output$
; P2.6 = ($$P2DIR.6$) $%tP2DIR.$Input$Output$
; P2.5 = ($$P2DIR.5$) $%tP2DIR.$Input$Output$
; P2.4 = ($$P2DIR.4$) $%tP2DIR.$Input$Output$
; P2.3 = ($$P2DIR.3$) $%tP2DIR.$Input$Output$
; P2.2 = ($$P2DIR.2$) $%tP2DIR.$Input$Output$
; P2.1 = ($$P2DIR.1$) $%tP2DIR.$Input$Output$
; P2.0 = ($$P2DIR.0$) $%tP2DIR.$Input$Output$
    Set186Register P2DIR, 0$$P2DIR$H
    ret
Init_IO_Port2   ENDP
_TEXT   ENDS
END
##80C186EB IO2#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
INCLUDE 186ebmem.inc
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
INCLUDE 186ebio.inc
$$END$
_TEXT    SEGMENT PUBLIC 'CODE'
    ASSUME CS:_TEXT
Init_IO_Port2   Proc
; P2.5/BCLK0  = ($$P2CON.5$) $%tP2CON.5$BLK0 Pin$I/O Pin$
; P2.4/CTS1   = ($$P2CON.4$) $%tP2CON.4$CTS1 Pin$I/O Pin$
; P2.3/SINT1  = ($$P2CON.3$) $%tP2CON.3$SINT1 Pin$I/O Pin$
; P2.2/BCLK1  = ($$P2CON.2$) $%tP2CON.2$BCLK1 Pin$I/O Pin$
; P2.1/TXD1   = ($$P2CON.1$) $%tP2CON.1$TxD1 Pin$I/O Pin$
; P2.0/RXD1   = ($$P2CON.0$) $%tP2CON.0$RxD1 Pin$I/O Pin$
    Set186Register P2CON, 0$$P2CON$H
;
; Initialize Port 2 Direction
;         Output = 1
; P2.7 = ($$P2DIR.7$) $%tP2DIR.7$Input$Output$