📄 186a.cod
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/*
* Copyright (c) 1995, Intel Corporation
*
* $Workfile: 186a.cod $
* $Revision: 1.1 $
* $Modtime: Mar 22 1995 16:53:36 $
*
* Purpose:
*
*
*
*
*
* Compiler:
*
* Ext Packages:
*
*
*
*/
##COMMENT#
************* Register Editor Coding information ************
##80C186E? WRITE#
##80C186XL WRITE#
$$IFSTR$ REG_MNEM "WDT????"
Use the Peripheral Editor
to Program @@REG_MNEM@
$$END$
$$ELSE$
$$IF$ REG_USEMACRO
Set186Register @@REG_MNEM@, $%aREG_VALUE$
$$END$
$$ELSE$
$$IFN$ RELREG.12
MOV DX, @@REG_MNEM@
MOV AX, $%aREG_VALUE$
OUT DX, AX
$$END$
$$IF$ RELREG.12
MOV ES, SEG @@REG_MNEM@
MOV ES:@@REG_MNEM@, $%aREG_VALUE$
$$END$
$$END$
$$END$
##80C186E? READ#
##80C186XL READ#
$$IFSTR$ REG_MNEM "WDT????"
Use the Peripheral Editor
to Program @@REG_MNEM@
$$END$
$$ELSE$
$$IF$ REG_USEMACRO
Get186Register @@REG_MNEM@
$$END$
$$ELSE$
$$IFN$ RELREG.12
MOV DX, @@REG_MNEM@
IN AX, DX
$$END$
$$IF$ RELREG.12
MOV ES, SEG @@REG_MNEM@
MOV AX, ES:@@REG_MNEM@
$$END$
$$END$
$$END$
##80C186E? AND#
##80C186XL AND#
$$IFSTR$ REG_MNEM "WDT????"
Use the Peripheral Editor
to Program @@REG_MNEM@
$$END$
$$ELSE$
$$IF$ REG_USEMACRO
Get186Register @@REG_MNEM@
AND AX, $%aREG_VALUE$
Set186RegisterAX @@REG_MNEM@
$$END$
$$ELSE$
$$IFN$ RELREG.12
MOV DX, @@REG_MNEM@
IN AX, DX
AND AX, $%aREG_VALUE$
OUT DX, AX
$$END$
$$IF$ RELREG.12
MOV ES, SEG @@REG_MNEM@
MOV AX, ES:@@REG_MNEM@
AND AX, $%aREG_VALUE$
MOV ES:@@REG_MNEM@ , AX
$$END$
$$END$
$$END$
##80C186E? XOR#
##80C186XL XOR#
$$IFSTR$ REG_MNEM "WDT????"
Use the Peripheral Editor
to Program @@REG_MNEM@
$$END$
$$ELSE$
$$IF$ REG_USEMACRO
Get186Register @@REG_MNEM@
XOR AX, $%aREG_VALUE$
Set186RegisterAX @@REG_MNEM@
$$END$
$$ELSE$
$$IFN$ RELREG.12
MOV DX, @@REG_MNEM@
IN AX, DX
XOR AX, $%aREG_VALUE$
OUT DX, AX
$$END$
$$IF$ RELREG.12
MOV ES, SEG @@REG_MNEM@
MOV AX, ES:@@REG_MNEM@
XOR AX, $%aREG_VALUE$
MOV ES:@@REG_MNEM@ , AX
$$END$
$$END$
$$END$
##80C186E? OR#
##80C186XL OR#
$$IFSTR$ REG_MNEM "WDT????"
Use the Peripheral Editor
to Program @@REG_MNEM@
$$END$
$$ELSE$
$$IF$ REG_USEMACRO
Get186Register @@REG_MNEM@
OR AX, $%aREG_VALUE$
Set186RegisterAX @@REG_MNEM@
$$END$
$$ELSE$
$$IFN$ RELREG.12
MOV DX, @@REG_MNEM@
IN AX, DX
OR AX, $%aREG_VALUE$
OUT DX, AX
$$END$
$$IF$ RELREG.12
MOV ES, SEG @@REG_MNEM@
MOV AX, ES:@@REG_MNEM@
OR AX, $%aREG_VALUE$
MOV ES:@@REG_MNEM@ , AX
$$END$
$$END$
$$END$
##80C186E? TESTZ#
##80C186XL TESTZ#
$$IFSTR$ REG_MNEM "WDT????"
Use the Peripheral Editor
to Program @@REG_MNEM@
$$END$
$$ELSE$
$$IF$ REG_USEMACRO
Get186Register @@REG_MNEM@
$$END$
$$ELSE$
$$IFN$ RELREG.12
MOV DX, @@REG_MNEM@
IN AX, DX
$$END$
$$IF$ RELREG.12
MOV ES, SEG @@REG_MNEM@
MOV AX, ES:@@REG_MNEM@
$$END$
$$END$
TEST AX, $%aREG_VALUE$
JZ <Dest. Label>
$$END$
##80C186E? TESTNZ#
##80C186XL TESTNZ#
$$IFSTR$ REG_MNEM "WDT????"
Use the Peripheral Editor
to Program @@REG_MNEM@
$$END$
$$ELSE$
$$IF$ REG_USEMACRO
Get186Register @@REG_MNEM@
$$END$
$$ELSE$
$$IFN$ RELREG.12
MOV DX, @@REG_MNEM@
IN AX, DX
$$END$
$$IF$ RELREG.12
MOV ES, SEG @@REG_MNEM@
MOV AX, ES:@@REG_MNEM@
$$END$
$$END$
TEST AX, $%aREG_VALUE$
JNZ <Dest. Label>
$$END$
##COMMENT#
********** Begin Peripheral Editor Coding **************
##80C186EC DMA0#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
INCLUDE 186ecmem.inc
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
INCLUDE 186ecio.inc
$$END$
_TEXT SEGMENT PUBLIC 'CODE'
ASSUME CS:_TEXT
Init_DMA0 Proc
; Initialize Source Address
; Source Address = @@D0SRC@
Set186Register D0SRCL,0$$D0SRCL$H
Set186Register D0SRCH, 0$$D0SRCH$H
;
; Initialize Destination Address
; Destination Address = @@D0DST@
Set186Register D0DSTL, 0$$D0DSTL$H
Set186Register D0DSTH, 0$$D0DSTH$H
;
; Initialize Transfer Count
Set186Register D0TC, 0$$D0TC$H
;
; Initialize DMA Control Register
; Destination Address is in $%tD0CON.15$Memory$I/O$ Space
; Destination Decrement = ($$D0CON.14$) $%tD0CON.14$Decrement$Off$
; Destination Increment = ($$D0CON.13$) $%tD0CON.13$Increment$Off$
; Source Address is in $%tD0CON.12$Memory$I/O$ Space
; Source Decrement = ($$D0CON.11$) $%tD0CON.11$Decrement$Off$
; Source Increment = ($$D0CON.10$) $%tD0CON.10$Increment$Off$
; Terminal Count $%eD0CON.9$
; Interrupt is $%eD0CON.8$
; Synchronization:
; 00 - Unsyn 01 - Src Syn 10 - Dest Syn
; Synchronization = $$D0CON.7$$$D0CON.6$
; Priority = ($$D0CON.5$) $%tD0CON.5$High$Low$
; Internal IDRQ Select = ($$D0CON.4$) $%eD0CON.4$
; Change Start Bit = ($$D0CON.2$) $%eD0CON.2$
; Start = ($$D0CON.1$) $%eD0CON.1$
; Word Transfer = ($$D0CON.0$) $%tD0CON.0$Word$Byte$ Trensfere
Set186Register D0CON, 0$$D0CON$H
;
; Initialize DMA Priority Register
; DMA Module A Priority = ($$DMAPRI.0$) Module $%tMDAPRI.0$A$B$ has high priority.
; Internal DMA Request for Module A = ($$DMAPRI.8$) $%tDMAPRI.8$Serial channel 0$Timer 2$
MOV CX, 0$$DMAPRI$H
AND CX, 0404H
OR CX, 0$$DMAPRI$H
Set186Register DMAPRI, CX
ret
Init_DMA0 ENDP
_TEXT ENDS
END
##80C186XL DMA0#
##80C186EA DMA0#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
INCLUDE 186eamem.inc
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
INCLUDE 186eaio.inc
$$END$
_TEXT SEGMENT PUBLIC 'CODE'
ASSUME CS:_TEXT
Init_DMA0 Proc
; Initialize Source Address
; Source Address = @@D0SRC@
Set186Register D0SRCL, 0$$D0SRCL$H
Set186Register D0SRCH, 0$$D0SRCH$H
;
; Initialize Destination Address
; Destination Address = @@D0DST@
Set186Register D0DSTL, 0$$D0DSTL$H
Set186Register D0DSTH, 0$$D0DSTH$H
;
; Initialize Transfer Count
Set186Register D0TC, 0$$D0TC$H
;
; Initialize DMA Control Register
; Destination Address Space Select = ($$D0CON.15$) $%tD0CON.15$Memory$I/O$ Space
; Destination Decrement = ($$D0CON.14$) $%tD0CON.14$Decrement$Off$
; Destination Increment = ($$D0CON.13$) $%tD0CON.13$Increment$Off$
; Source Address Space Select = ($$D0CON.12$) $%tD0CON.12$Memory$I/O$ Space
; Source Decrement = ($$D0CON.11$) $%tD0CON.11$Decrement$Off$
; Source Increment = ($$D0CON.10$) $%tD0CON.10$Incremant$Off$
; Terminal Count = ($$D0CON.9$) $%eD0CON.9$
; Interrupt = ($$D0CON.8$) $%eD0CON.8$
; Synchronization:
; 00 - Unsyn 01 - Src Syn 10 - Dest Syn
; Synchronization = $$D0CON.7$$$D0CON.6$
; Priority = ($$D0CON.5$) $%tD0CON.5$High$Low$
; Internal IDRQ Select = ($$D0CON.4$) $%eD0CON.4$
; Change Start Bit = ($$D0CON.2$) $%eD0CON.2$
; Start = ($$D0CON.1$) $%eD0CON.1$
; Word Transfer = ($$D0CON.0$) $%tD0CON.0$Word$Byte$ Transfere
Set186Register D0CON, 0$$D0CON$H
ret
Init_DMA0 ENDP
_TEXT ENDS
END
##80C186EC DMA1#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
INCLUDE 186ecmem.inc
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
INCLUDE 186ecio.inc
$$END$
_TEXT SEGMENT PUBLIC 'CODE'
ASSUME CS:_TEXT
Init_DMA1 Proc
; Initialize Source Address
; Source Address = @@D1SRC@
Set186Register D1SRCL, 0$$D1SRCL$H
Set186Register D1SRCH, 0$$D1SRCH$H
;
; Initialize Destination Address
; Destination Address = @@D1DST@
Set186Register D1DSTL, 0$$D1DSTL$H
Set186Register D1DSTH, 0$$D1DSTH$H
;
; Initialize Transfer Count
Set186Register D1TC, 0$$D1TC$H
;
; Initialize DMA Control Register
; Destination Address Space Select = ($$D1CON.15$) $%tD1CON.15$Memory$I/O$ Space
; Destination Decrement = ($$D1CON.14$) $%tD1CON.14$Decrement$Off$
; Destination Increment = ($$D1CON.13$) $%tD1CON.13$Increment$Off$
; Source Address Space Select = ($$D1CON.12$) $%tD1CON.12$Memory$I/O$ Space
; Source Decrement = ($$D1CON.11$) $%tD1CON.11$Decrement$Off$
; Source Increment = ($$D1CON.10$) $%tD1CON.10$Increment$Off$
; Terminal Count = ($$D1CON.9$) $%eD1CON.9$
; Interrupt = ($$D1CON.8$) $%eD1CON.8$
; Synchronization:
; 00 - Unsyn 01 - Src Syn 10 - Dest Syn
; Synchronization = $$D1CON.7$$$D1CON.6$
; Priority = ($$D1CON.5$) $%tD1CON.5$High$Low$
; Internal IDRQ Select = ($$D1CON.4$) $%eD1CON.4$
; Change Start Bit = ($$D1CON.2$) $%eD1CON.2$
; Start = ($$D1CON.1$) $%eD1CON.1$
; Word Transfer = ($$D1CON.0$) $%tD1CON.0$Word$Byte$ Transfere
Set186Register D1CON, 0$$D1CON$H
;
; Initialize DMA Priority Register
; DMA Module A Priority = ($$DMAPRI.0$) $%tDMAPRI.0$High$Low$
; Internal DMA Request for Module A = ($$DMAPRI.8$) $%tDMAPRI.8$Serial Channel 0$Timer 2$
MOV CX, 0$$DMAPRI$H
AND CX, 0404H
OR CX, 0$$DMAPRI$H
Set186Register DMAPRI, CX
ret
Init_DMA1 ENDP
_TEXT ENDS
END
##80C186XL DMA1#
##80C186EA DMA1#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
INCLUDE 186eamem.inc
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
INCLUDE 186eaio.inc
$$END$
_TEXT SEGMENT PUBLIC 'CODE'
ASSUME CS:_TEXT
Init_DMA1 Proc
; Initialize Source Address
; Source Address = @@D1SRC@
Set186Register D1SRCL, 0$$D1SRCL$H
Set186Register D1SRCH, 0$$D1SRCH$H
;
; Initialize Destination Address
; Destination Address = @@D1DST@
Set186Register D1DSTL, 0$$D1DSTL$H
Set186Register D1DSTH, 0$$D1DSTH$H
;
; Initialize Transfer Count
Set186Register D1TC, 0$$D1TC$H
;
; Initialize DMA Control Register
; Destination Address Space Select = ($$D1CON.15$) $%tD1CON.15$Memory$I/O$ Space
; Destination Decrement = ($$D1CON.14$) $%tD1CON.14$Decrement$Off$
; Destination Increment = ($$D1CON.13$) $%tD1CON.13$Increment$Off$
; Source Address Space Select = ($$D1CON.12$) $%tD1CON.12$Memory$I/O$ Space
; Source Decrement = ($$D1CON.11$) $%tD1CON.11$Decrement$Off$
; Source Increment = ($$D1CON.10$) $%tD1CON.10$Increment$Off$
; Terminal Count = ($$D1CON.9$) $%eD1CON.9$
; Interrupt = ($$D1CON.8$) $%eD1CON.8$
; Synchronization:
; 00 - Unsyn 01 - Src Syn 10 - Dest Syn
; Synchronization = $$D1CON.7$$$D1CON.6$
; Priority = ($$D1CON.5$) $%tD1CON.5$High$Low$
; Internal IDRQ Select = ($$D1CON.4$) $%eD1CON.4$
; Change Start Bit = ($$D1CON.2$) $%eD1CON.2$
; Start = ($$D1CON.1$) $%eD1CON.1$
; Word Transfer = ($$D1CON.0$) $%tD1CON.0$Word$Byte$ Transfere
Set186Register D1CON, 0$$D1CON$H
ret
Init_DMA1 ENDP
_TEXT ENDS
END
##80C186EC DMA2#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
INCLUDE 186ecmem.inc
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
INCLUDE 186ecio.inc
$$END$
_TEXT SEGMENT PUBLIC 'CODE'
ASSUME CS:_TEXT
Init_DMA2 Proc
; Initialize Source Address
; Source Address = @@D2SRC@
Set186Register D2SRCL, 0$$D2SRCL$H
Set186Register D2SRCH, 0$$D2SRCH$H
;
; Initialize Destination Address
; Destination Address = @@D2DST@
Set186Register D2DSTL, 0$$D2DSTL$H
Set186Register D2DSTH, 0$$D2DSTH$H
;
; Initialize Transfer Count
Set186Register D2TC, 0$$D2TC$H
;
; Initialize DMA Control Register
; Destination Address Space Select = ($$D2CON.15$) $%tD2CON.15$Memory$I/O$ Space
; Destination Decrement = ($$D2CON.14$) $%tD2CON.14$Decrement$Off$
; Destination Increment = ($$D2CON.13$) $%tD2CON.13$Incremant$Off$
; Source Address Space Select = ($$D2CON.12$) $%tD2CON.12$Memory$I/O$ Space
; Source Decrement = ($$D2CON.11$) $%tD2CON.11$Decrement$Off$
; Source Increment = ($$D2CON.10$) $%tD2CON.10$Increment$Off$
; Terminal Count = ($$D2CON.9$) $%eD2CON.9$
; Interrupt = ($$D2CON.8$) $%eD2CON.8$
; Synchronization:
; 00 - Unsyn 01 - Src Syn 10 - Dest Syn
; Synchronization = $$D2CON.7$$$D2CON.6$
; Priority = ($$D2CON.5$) $%tD2CON.5$High$Low$
; Internal IDRQ Select = ($$D2CON.4$) $%eD2CON.4$
; Change Start Bit = ($$D2CON.2$) $%eD2CON.2$
; Start = ($$D2CON.1$) $%eD2CON.1$
; Word Transfer = ($$D2CON.0$) $%tD2CON.0$Word$Byte$ Transfere
Set186Register D2CON, 0$$D2CON$H
;
; Initialize DMA Priority Register
; DMA Module B Priority = ($$DMAPRI.2$) $%tDMAPRI.2$High$Low$
; Internal DMA Request for Module B = ($$DMAPRI.10$) $%tDMAPRI.10$Serial Channel 1$Timer 2$
MOV CX, 0$$DMAPRI$H
AND CX, 0101H
OR CX, 0$$DMAPRI$H
Set186Register DMAPRI, CX
ret
Init_DMA2 ENDP
_TEXT ENDS
END
##80C186EC DMA3#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
INCLUDE 186ecmem.inc
$$END$
$$IFN$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-7$00H
INCLUDE 186ecio.inc
$$END$
_TEXT SEGMENT PUBLIC 'CODE'
ASSUME CS:_TEXT
Init_DMA3 Proc
; Initialize Source Address
; Source Address = @@D3SRC@
Set186Register D3SRCL, 0$$D3SRCL$H
Set186Register D3SRCH, 0$$D3SRCH$H
;
; Initialize Destination Address
; Destination Address = @@D3DST@
Set186Register D3DSTL, 0$$D3DSTL$H
Set186Register D3DSTH, 0$$D3DSTH$H
;
; Initialize Transfer Count
Set186Register D3TC, 0$$D3TC$H
;
; Initialize DMA Control Register
; Destination Address Space Select = ($$D3CON.15$) $%tD3CON.15$Memory$I/O$ Space
; Destination Increment = ($$D3CON.13$) $%tD3CON.13$Increment$Off$
; Destination Decrement = ($$D3CON.14$) $%tD3CON.14$Decrement$Off$
; Source Address Space Select = ($$D3CON.12$) $%tD3CON.12$Memory$I/O$ Space
; Source Decrement = ($$D3CON.11$) $%tD3CON.11$Decrement$Off$
; Source Increment = ($$D3CON.10$) $%tD3CON.10$Increment$Off$
; Terminal Count = ($$D3CON.9$) $%eD3CON.9$
; Interrupt = ($$D3CON.8$) $%eD3CON.8$
; Synchronization:
; 00 - Unsyn 01 - Src Syn 10 - Dest Syn
; Synchronization = $$D3CON.7$$$D3CON.6$
; Priority = ($$D3CON.5$) $%tD3CON.5$High$Low$
; Internal IDRQ Select = ($$D3CON.4$) $%eD3CON.4$
; Change Start Bit = ($$D3CON.2$) $%eD3CON.2$
; Start = ($$D3CON.1$) $%eD3CON.1$
; Word Transfer = ($$D3CON.0$) $%tD3CON.0$Word$Byte$ Transfere
Set186Register D3CON, 0$$D3CON$H
;
; Initialize DMA Priority Register
; DMA Module B Priority = ($$DMAPRI.2$) $%tDMAPRI.2$High$Low$
; Internal DMA Request for Module B = ($$DMAPRI.10$) $%tDMAPRI.10$Serial Channel 1$Timer 2$
MOV CX, 0$$DMAPRI$H
AND CX, 0101H
OR CX, 0$$DMAPRI$H
Set186Register DMAPRI, CX
ret
Init_DMA3 ENDP
_TEXT ENDS
END
##80C186EC Timer2#
##80C186EB Timer2#
##80C186XL Timer2#
##80C186EA Timer2#
$$IF$ RELREG.12
PCB_BASE EQU 0$$RELREG.0-11$00H
$$IFP$ 80C186EC
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